Vertical Memory Gate-Line Layout for Simpler 3D Signal Routing
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Solution Overview
Problem
Vertical memory devices face challenges in efficiently applying electrical signals to memory cells stacked in a three-dimensional structure, requiring complex pad structures that complicate integration and scalability.
Innovation Solution
The design includes a gate line structure with sequentially stacked gate lines and vertical channel structures, featuring connection regions with protrusions that facilitate electrical connections and reduce complexity, allowing for efficient signal application and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are vertically stacked in three dimensions to increase integration, then storage capacity is improved, but pad structure complexity increases
Solution Approach 1:
The patent transitions from planar pad structures to three-dimensional protrusion structures that extend vertically. Multiple protrusions are formed at different heights corresponding to different gate line layers, enabling vertical stacking of connection points without increasing lateral pad area. This dimensional transition resolves the contradiction by maintaining high integration while managing pad structure complexity through vertical organization.
Solution Approach 2:
The patent implements a nested structure where protrusions from multiple gate line layers are vertically aligned and nested within the same lateral footprint. Each protrusion corresponds to a specific gate line layer, creating a nested arrangement where connection points are stacked vertically. This nesting approach allows multiple connection points to share the same space, reducing overall pad structure complexity while maintaining high storage capacity.
2Quantity of substance
If multiple gate lines are stacked vertically to increase integration, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate line structure into multiple distinct layers, with each layer forming protrusions at specific vertical positions. This segmentation allows independent formation and control of each gate line layer and its corresponding protrusions, simplifying the manufacturing process by breaking down the complex vertical stacking into manageable discrete steps rather than requiring simultaneous multi-layer alignment.
Solution Approach 2:
The patent employs preliminary formation of protrusions for each gate line layer before final assembly. By pre-forming the protrusion structures at each layer and then stacking the layers, the manufacturing process is simplified. This preliminary action approach allows each layer to be prepared and verified independently, reducing the overall manufacturing complexity of the vertically stacked multi-layer structure.
3Productivity
If connection regions are designed with multiple protrusions for vertical stacking, then signal application efficiency is improved, but device complexity increases
Solution Approach 1:
The patent designs the protrusion structures to serve multiple functions: they act as connection points for electrical signals, define the vertical positioning of gate line layers, and provide alignment references for stacking. This multi-functionality reduces the need for separate dedicated structures, thereby improving signal application efficiency without proportionally increasing device complexity. The same protrusion features accomplish multiple objectives simultaneously.
Solution Approach 2:
The patent merges the connection region design with the gate line structure itself, where the protrusions are integral parts of the gate lines rather than separate components. By combining the connection functionality directly into the gate line structures, the patent reduces overall device complexity while maintaining efficient signal application. The merged design eliminates the need for separate connection elements, achieving both goals simultaneously.
Data Source
AI summary
A vertical memory device includes a gate line structure including a cell region in which a vertical channel structure is formed, and a first connection region and a second connection region which are respectively arranged at first and second ends of the cell region in a first direction. Each of the first connection region and the second connection region includes a first protrusion of the first gate line and a second protrusion of the second gate line which are parallel to a top surface of the substrate and arranged as steps in a second direction perpendicular to the first direction. The first protrusion of the second connection region is arranged diagonally from the first protrusion of the first connection region with respect to a center line of the cell region which is parallel to the first direction.