Vertical Memory Devices Preventing Gate Voids
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Solution Overview
Problem
In the manufacturing of vertical memory devices, the close proximity of channels leads to void formation during the gate electrode layer formation process, resulting in insufficient space for bit lines and reduced integration density.
Innovation Solution
The design incorporates multiple cylindrical-shaped channel regions with vertically-stacked gate electrodes and a charge storage layer on the substrate, along with conductive patterns and bit lines arranged in a specific configuration to increase integration density and prevent void formation during gate electrode deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If channels are disposed adjacent to each other to increase integration density, then the degree of integration is improved, but voids occur during gate electrode layer formation and space for bit lines becomes insufficient
Solution Approach 1:
The gate electrode layer formation process is segmented into multiple steps with intermediate treatments. Specifically, the gate electrode is formed in a first region, then a first insulation layer is formed to separate it from the second region where the next gate electrode will be formed. This segmentation prevents void formation by ensuring proper isolation and spacing between adjacent gate electrodes while maintaining high channel density.
Solution Approach 2:
The first insulation layer is formed preliminarily between adjacent gate electrode regions before the second gate electrode is formed. This preliminary action ensures that adequate space is reserved for bit lines and prevents void formation during subsequent processing steps, allowing high integration density to be achieved without manufacturing defects.
2Quantity of substance
If channels are disposed adjacent to each other to increase integration density, then the degree of integration is improved, but space for receiving bit lines becomes insufficient
Solution Approach 1:
The problem of insufficient space for bit lines is resolved by utilizing the vertical dimension. Multiple gate electrodes are stacked vertically in a columnar structure, which frees up horizontal space that can then be allocated for bit line routing. This dimensional transition allows high integration density to be achieved without compromising the space available for bit lines.
Solution Approach 2:
The device structure is segmented into distinct functional regions: a first region for source/drain electrodes, a second region for gate electrodes with intervening insulation layers, and spaces allocated for bit lines. This segmentation allows each component to be optimally positioned, ensuring adequate space for bit lines while maintaining high integration density through vertical stacking of gate electrodes.
Data Source
AI summary
Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.