Vertical Memory Structures with Isolation Trenches
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high element density and large memory capacity while maintaining a small size, as they struggle to efficiently utilize space and improve program and erase speeds.
Innovation Solution
A semiconductor structure with vertical memory structures having horizontal C-shaped cross sections and separated by an isolation trench, where conductive layers and dielectric layers are interlaced, and a manufacturing method that involves forming memory structures with distinct etching selectivity protecting structures, allowing for increased memory density and efficient stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory structures are arranged in traditional planar configuration, then manufacturing process is simple, but memory density per unit area is low
Solution Approach 1:
The patent transitions from traditional planar memory arrangement to a three-dimensional vertical structure with C-shaped cross-sections. Multiple memory structures are stacked vertically and separated by isolation trenches, utilizing the third dimension (vertical space) to increase memory density per unit area without proportionally increasing manufacturing complexity
Solution Approach 2:
The memory structure is divided into multiple C-shaped segments stacked vertically, with isolation trenches separating adjacent structures. This segmentation allows independent formation and processing of each segment while achieving high overall density through the stacked configuration
2Speed
If conventional insulating layers are used, then manufacturing process is straightforward, but program and erase speeds are limited due to higher resistance
Solution Approach 1:
The patent changes the electrical parameter of the interlayer material from insulating (high resistance) to conductive (low resistance). This parameter change directly improves program and erase speeds by reducing resistance, while the manufacturing process remains similar by replacing insulating layers with conductive layers at specific stages
Solution Approach 2:
The conductive layers serve multiple functions: they act as interconnects for electrical signaling, provide low-resistance pathways for fast programming and erasing, and maintain the layered structural organization. This multi-functionality achieves speed improvement without significantly complicating the manufacturing process
3Quantity of substance
If memory structures are placed closer together to increase density, then storage capacity per unit area increases, but manufacturing precision requirements increase
Solution Approach 1:
Isolation trenches are introduced as intermediary structures between adjacent C-shaped memory structures. These trenches provide physical separation and spacing control, enabling high-density placement of memory structures while maintaining manufacturable precision through the mediating isolation features
Solution Approach 2:
The C-shaped cross-section of memory structures provides curved geometry that optimizes space utilization. The curved configuration allows structures to be packed more efficiently compared to straight linear arrangements, increasing storage capacity while maintaining reasonable spacing and manufacturing precision
Data Source
AI summary
A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.