Vertical Memory Pillar Fabrication via Peripheral Segmentation
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Solution Overview
Problem
The miniaturization of semiconductor memory devices is limited by the difficulty in precisely controlling the planarization process due to the large height difference between the cell and peripheral areas in vertical memory devices, leading to challenges in forming lower electrodes with high aspect ratios and affecting yield and integration.
Innovation Solution
A semiconductor memory apparatus and fabrication method where the semiconductor substrate is recessed to form pillars in the cell area and a recessed part in the peripheral area, allowing the core switching device to be formed in the recessed part, thereby reducing the height of the core switching device and allowing for more precise control of the planarization process and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the core switching device is formed high in a multi-layered structure to enable vertical memory device formation, then the memory device can be formed with sufficient height, but the planarization process becomes difficult to control precisely due to large height difference between cell area and peripheral area
Solution Approach 1:
The peripheral area is divided into two distinct levels: a first level with the core switching device and a second level with a filler structure. This segmentation allows each region to be optimized independently - the core switching device can be formed at the required height while the filler compensates for height differences to enable precise planarization of the upper surface.
Solution Approach 2:
A filler structure is introduced as an intermediary element in the peripheral area. This filler acts as a height-compensating mediator that fills the space between the core switching device and the upper surface, enabling precise planarization without affecting the core switching device functionality while allowing accurate formation of lower electrodes.
2Ease of manufacture
If the peripheral area is not recessed and maintains initial height to simplify fabrication, then the fabrication process is simpler, but the height of upper surface in peripheral area becomes higher than in cell area creating stepped structure
Solution Approach 1:
The peripheral area is segmented into functional zones at different heights - the core switching device region and the filler region. This segmentation allows the upper surface to be planarized at a uniform height while the core switching device maintains its required height, eliminating the stepped structure between cell and peripheral areas.
Solution Approach 2:
The solution transitions from a single-level peripheral area to a multi-level structure by adding vertical dimensionality. The filler structure creates a second level that compensates for height differences, transforming the stepped surface into a uniform upper surface while preserving the core switching device height.
3Reliability
If lower electrode contact hole is formed by patterning interlayer insulating layer with large aspect ratio, then lower electrode can be formed, but the process difficulty increases and yield decreases
Solution Approach 1:
The filler structure serves as an intermediary that eliminates the need for deep contact holes through the interlayer insulating layer. By providing a height-matched region in the peripheral area, the lower electrode can be formed with reduced aspect ratio, simplifying the patterning and filling processes while improving yield.
Solution Approach 2:
The aspect ratio parameter of the lower electrode contact hole is changed from large to small by utilizing the filler structure. This parameter change transforms the formation process from difficult to straightforward, enabling standard patterning and filling techniques to be used effectively.
Data Source
AI summary
Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part.