Vertical Memory Device Sacrificial Layer Thermal Stress
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Solution Overview
Problem
Existing vertical memory device manufacturing methods face challenges in achieving high integration and reliability due to misalignment and deformation issues caused by thermal stress from nitride-based sacrificial layers, which affect the etching process and structural integrity.
Innovation Solution
The method involves alternately stacking insulating and sacrificial layers, with polysilicon or amorphous silicon used as sacrificial layers, allowing for selective removal without damaging insulating interlayers and reducing thermal stress, thereby preventing misalignment and deformation, and forming gate lines and supporting patterns to enhance device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If nitride-based sacrificial layers are used in vertical memory device manufacturing, then the sacrificial layers provide structural support during fabrication, but thermal stress causes misalignment and deformation affecting etching precision and device reliability
Solution Approach 1:
The patent changes the material parameter of sacrificial layers from nitride-based materials to oxide-based materials (such as silicon oxide). This material substitution fundamentally alters the thermal and mechanical properties, eliminating thermal stress accumulation during fabrication while maintaining the structural support function needed for precise etching and device formation.
Solution Approach 2:
The patent employs sacrificial layers as temporary, disposable structures that are intentionally designed to be removed after serving their structural support purpose during fabrication. These oxide-based sacrificial layers enable precise pattern formation during etching, then are completely removed to leave clean gaps for gate line formation, eliminating the need for complex stress management.
2Stability of the object's composition
If nitride-based sacrificial layers are used, then the sacrificial layers maintain structural integrity during fabrication, but thermal stress leads to deformation reducing device reliability
Solution Approach 1:
The patent changes the material composition parameter from nitride-based to oxide-based sacrificial layers. This substitution fundamentally improves device reliability by eliminating thermal stress-induced deformation while maintaining structural integrity throughout the fabrication process, ensuring consistent device performance.
3Ease of manufacture
If polysilicon or amorphous silicon is used as sacrificial layers, then selective removal is enabled without damaging insulating interlayers, but additional process steps are required for precise removal
Solution Approach 1:
The patent employs composite material structures where oxide-based sacrificial layers are combined with insulating interlayers having different etch selectivity. This allows the sacrificial layers to be selectively removed using specific etchants that do not damage the insulating interlayers, achieving easy selective removal while maintaining process simplicity through natural material compatibility.
4Productivity
If vertical stacking of insulating and sacrificial layers is performed, then high degree of integration is achieved, but thermal stress accumulation increases causing misalignment
Solution Approach 1:
The patent changes the material parameter of sacrificial layers to oxide-based materials that do not generate thermal stress during fabrication. This enables the vertical stacking of multiple insulating and sacrificial layers to achieve high integration density while maintaining precise alignment throughout the stacked structure, as no thermal stress accumulates to cause misalignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of compact and reliable vertical memory devices with improved integration and reduced thermal stress, ensuring accurate etching and structural integrity, thus enhancing device performance and reliability.
Implementation Method 1
The sacrificial layers are removed by a gas phase etching process using a chlorine gas or a wet etching process using an etchant solution that contains a hydroxyl group.
Data Source
AI summary
A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.