Vertical Memory Devices With Segmented Charge Trapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a limit to scaling down vertical memory devices due to challenges in reducing the size of each layer, which affects the degree of integration and electrical characteristics.
Innovation Solution
The design includes gate electrodes with a tunnel insulation pattern and a charge trapping pattern structure on the outer sidewall of the channel, featuring upper and lower charge trapping patterns spaced apart, along with a blocking pattern to enhance integration and electrical efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of each layer is reduced to increase integration degree, then the degree of integration is improved, but manufacturing precision and process control become more difficult
Solution Approach 1:
The charge trapping layer is segmented into multiple distinct regions (first charge trapping region, second charge trapping region, third charge trapping region) along the vertical direction. This segmentation allows each region to be independently controlled and optimized, enabling better precision in a vertically stacked configuration rather than horizontally scaling, thus resolving the contradiction between integration and manufacturing precision.
Solution Approach 2:
The patent transitions from horizontal scaling to vertical stacking by arranging multiple charge trapping regions and gate electrodes in the vertical direction. This dimensional change allows increased integration degree without requiring further reduction in lateral dimensions, thereby avoiding the manufacturing precision limitations associated with scaling down layer sizes.
2Reliability
If multiple charge trapping patterns are added to improve electron injection efficiency, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
Multiple charge trapping regions are merged into a single vertical stack structure that shares common tunnel insulation patterns and blocking patterns. The first, second, and third charge trapping regions are positioned between alternating gate electrodes and insulation patterns, forming an integrated vertical architecture. This merging approach achieves improved electron injection through multiple trapping regions while avoiding the complexity of separate horizontal structures.
Solution Approach 2:
The patent resolves the complexity issue by arranging multiple charge trapping patterns in the vertical dimension rather than lateral dimensions. The stacked configuration allows multiple electron injection pathways to be achieved through vertical layering, maintaining structural efficiency and simplifying interconnections compared to horizontal arrangements.
3Quantity of substance
If gate electrodes are placed closer together to increase integration, then integration degree is improved, but interference between gate electrodes increases
Solution Approach 1:
Alternating insulation patterns are positioned between adjacent gate electrodes in the vertical stack, serving as intermediary structures that electrically isolate neighboring gate electrodes. This intermediary configuration allows gate electrodes to be placed in close proximity for high integration while preventing harmful electromagnetic interference and crosstalk between adjacent gates.
Solution Approach 2:
The vertical structure is segmented into alternating layers of gate electrodes and insulation patterns, creating discrete electrical zones. This segmentation physically separates the electrical fields of adjacent gate electrodes, reducing interference while maintaining compact vertical integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the integration degree and electrical characteristics of vertical memory devices by efficiently injecting electrons through multiple charge trapping patterns, while minimizing interference between gate electrodes.
Implementation Method 1
A tunnel insulation pattern is formed on an outer sidewall of the channel
Data Source
AI summary
A vertical memory device includes gate electrodes on a substrate. The gate electrodes are spaced apart from each other in a vertical direction. A channel penetrates the gate electrodes and extends in the vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent the gate electrodes in a horizontal direction. The charge trapping pattern structure includes upper and lower charge trapping patterns. A blocking pattern is formed between the charge trapping pattern structure and each of the adjacent gate electrodes. An upper surface of the upper charge trapping pattern is higher than an upper surface of the adjacent gate electrode. A lower surface of the lower charge trapping pattern is lower than a lower surface of an adjacent gate electrode.