2-Transistor Vertical Memory Cells With Shared Channels for Dense Storage
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density due to physical limitations and fabrication constraints when shrinking memory cell size, and they often require multiple access lines for read and write operations, which complicates the device structure.
Innovation Solution
A memory device with 2-transistor vertical memory cells that utilize a shared channel region and a floating-gate structure, allowing for a compact 4F2 cell footprint and improved storage density, with a single access line controlling both transistors for simplified operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk to increase storage density, then storage density is improved, but physical limitations and fabrication constraints make it difficult to achieve further shrinkage
Solution Approach 1:
The patent transitions from planar (2D) memory cell layout to vertical (3D) stacking architecture. Multiple memory cells are stacked vertically along the Z-axis, allowing increased storage density without further shrinking the footprint area. This dimensional change enables more cells to be packed into the same device area while avoiding the fabrication constraints associated with lateral scaling.
Solution Approach 2:
The patent implements nested structures where multiple memory cells share common access lines and control circuits. The vertical stacking allows inner cells to be nested within the structural framework established by outer cells, with shared channel regions and access lines serving multiple cells simultaneously, thereby reducing overall device complexity while increasing density.
2Adaptability or versatility
If multiple access lines are used for read and write operations, then operational functionality is improved, but device structure becomes more complex
Solution Approach 1:
The patent designs access lines that serve multiple functions: the same access line can be used for both read and write operations, and can access multiple memory cells in the vertical stack through time-multiplexed control signals. This multi-functionality reduces the total number of access lines required while maintaining full operational capability.
Solution Approach 2:
The patent employs dynamic control mechanisms where access lines are selectively activated for different memory cells based on time-multiplexed signals. The access lines transition between different functional states (reading from one cell, writing to another, accessing different vertical levels) rather than being statically dedicated to single functions, thereby reducing structural complexity.
3Quantity of substance
If vertical memory cells with shared channel region are used, then storage density and reduced power dissipation are achieved, but transistor control complexity increases
Solution Approach 1:
The patent merges the control functions for multiple transistors into shared control lines. The shared channel region is controlled by a common access line that can be selectively activated to control different transistor pairs in the vertical stack. This combining of control functions reduces the number of separate control signals required while enabling precise access to individual cells.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.