Vertical Memory Gate Staircase With Shared Contact Plug and Through Via

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Solution Overview

Problem

The existing methods for manufacturing VNAND flash memory devices face challenges in efficiently forming contact plugs to contact vertically stacked gate electrodes, leading to increased process time and cost, and require separate processes for contact plugs and through vias.

Innovation Solution

A vertical memory device design where contact plugs and through vias are formed using the same etching and deposition processes, with the contact plugs extending through gate electrode structures and being electrically connected to only one gate electrode at a certain level, and the gate electrode structures are formed using overlapping first and second molds to reduce the horizontal area and processing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate processes are used for forming contact plugs and through vias, then the electrical connection reliability is improved, but the manufacturing time and cost increase

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmanufacturing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines the formation of contact plugs and through vias into a single integrated process. The contact plug structure is formed within the through via using the same etching and deposition processes, eliminating the need for separate manufacturing steps while maintaining electrical connection reliability between vertically stacked gate electrodes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The through via structure serves multiple functions simultaneously: it acts as both a through via for electrical connection and as a contact plug structure. The conductive material filling the through via provides both the via connection and the contact plug function, reducing process complexity and manufacturing time.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If overlapping first and second molds are used to form gate electrode structures, then the horizontal area is reduced, but the process complexity increases

Engineering Contradiction:
Improvehorizontal areaVSAvoidprocess complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent employs a nested mold structure where a first mold and a second mold are overlapped vertically to form gate electrode structures at different heights. The first mold forms gate electrodes in a first region, while the second mold forms gate electrodes in a second region, with the molds nested or overlapped in the vertical direction. This nesting approach reduces the horizontal footprint while systematically managing the increased process complexity through structured, sequential fabrication steps.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Adaptability or versatility

If contact plugs extend through multiple gate electrode structures, then the electrical connection versatility is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connection versatilityVSAvoidetching and deposition precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent implements selective electrical connections where contact plugs are configured to connect to specific gate electrodes at specific levels rather than all gate electrodes uniformly. The etching and deposition processes are localized to create contact plugs that extend through selected gate electrode structures, with protrusion portions making contact with particular gate electrodes. This local quality approach provides connection versatility while managing precision requirements through targeted, rather than universal, high-precision operations.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11895838B2Vertical memory devices
Publication Date: 2024.02.06 SAMSUNG ELECTRONICS CO LTD
  • US11895838B2 patent drawing
  • US11895838B2 patent drawing
  • US11895838B2 patent drawing

AI summary

A vertical memory device includes a first gate structure on a substrate, the first gate structure including first gate electrodes spaced from each other in a first direction and stacked in a staircase shape, a second gate structure on the first gate structure and including second gate electrodes spaced from each other in the first direction and stacked in the staircase shape, a channel extending through the first and second gate structures, and a contact plug extending in the first direction through the first and second gate structures, wherein second steps at end portions of the second gate electrodes overlap first steps at end portions of the first gate electrodes, and wherein the contact plug extends through at least one of the first steps and through at least one of the second steps, while being electrically connected only to the first steps or to the second steps.