3D Non-Volatile Memory Stack for Density and Speed Tradeoffs
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and maintaining high operation speed while minimizing the two-dimensional area footprint.
Innovation Solution
A non-volatile memory device with a three-dimensional structure featuring vertically arranged memory cells, including a stack structure with alternating gate layers and insulating layers, and anti-fuse structures connected via resistance structures for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional flash memory semiconductor devices with vertically arranged memory cells are used, then data storage capacity is increased, but operation speed may be reduced due to increased signal transmission distance
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional memory cell arrangement, stacking multiple memory cells vertically along the third dimension. This dimensional change increases storage capacity while maintaining high operation speed through optimized vertical interconnect structures and resistance structures that enable efficient signal transmission between stacked memory cells and control circuits.
2Quantity of substance
If three-dimensional flash memory semiconductor devices with vertically arranged memory cells are used, then data storage capacity is increased, but the device occupies larger two-dimensional area
Solution Approach 1:
The patent implements vertical stacking of memory cells along the third dimension, transforming the area utilization from two-dimensional expansion to three-dimensional utilization. This reduces the two-dimensional footprint while increasing storage capacity through the vertical arrangement of multiple memory cells sharing common word lines and bit lines.
Solution Approach 2:
The patent merges multiple memory cells into vertical strings that share common control lines and interconnect structures. By combining multiple memory cells in a stacked configuration, the device achieves higher capacity while minimizing the planar area occupied, as multiple cells occupy the same footprint in the vertical dimension.
3Reliability
If anti-fuse structures are connected via resistance structures, then electrical connectivity is enhanced, but device complexity increases
Solution Approach 1:
The patent introduces resistance structures as intermediary conductive paths between anti-fuse structures and control circuits. These resistance structures serve as mediators that enable reliable electrical connectivity while providing controlled resistance characteristics. The resistance structures are integrated into the stack structure, allowing multiple anti-fuse structures to be connected through a shared resistive pathway, which manages complexity through systematic integration.
Data Source
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AI summary
A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.