Vertical Memory Stack Interconnection for High Integration
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Solution Overview
Problem
As information communication apparatuses become more multifunctional, there is a need for integrated circuit devices with increased capacity and integration, particularly in memory devices, where the complexity of operation circuits and wiring structures due to reduced memory cell sizes poses challenges in achieving improved electrical characteristics and higher integration while maintaining a compact chip size.
Innovation Solution
The integrated circuit device features a vertical memory structure with stacked word lines, contact plugs, and interconnection layers arranged at different vertical levels, allowing for a reduced chip area and improved interconnection flexibility, enabling higher integration without increasing process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of word lines stacked is increased to obtain higher integration, then the degree of integration is improved, but the complexity of operation circuits and wiring structures increases
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical stacking, where word lines are arranged in multiple stacked layers (first through fourth word lines at different heights) with corresponding contact plugs and interconnection layers connecting them vertically. This dimensional change allows higher integration without proportionally increasing wiring complexity, as the vertical arrangement naturally organizes the interconnection structure.
Solution Approach 2:
The memory device is divided into distinct functional segments: memory cell regions with stacked word lines, separate connection regions for interconnections, and peripheral circuit regions. This segmentation allows independent optimization of each region, reducing overall system complexity while maintaining high integration in the memory cell area.
2Productivity
If memory cell size is reduced for higher integration, then the degree of integration is improved, but the electrical characteristics deteriorate
Solution Approach 1:
The patent employs multiple parameter changes to maintain electrical characteristics while achieving higher integration: using different material compositions for tunnel barriers (oxide layers) and charge storage layers (nitride layers) to optimize charge injection and retention; adjusting the thickness parameters of each layer to control electrical properties; and varying the doping concentrations in semiconductor regions to maintain carrier mobility and threshold voltage despite reduced cell dimensions.
3Productivity
If the number of contacts connected to word lines and interconnections are increased, then the degree of integration is improved, but the chip area increases
Solution Approach 1:
The patent utilizes vertical stacking to arrange multiple word lines and their corresponding contact plugs and interconnection layers in the vertical dimension rather than spreading them out horizontally. This allows a large number of contacts and interconnections to be accommodated within a compact chip footprint by exploiting the third dimension, thereby increasing integration without proportionally increasing chip area.
Solution Approach 2:
The structure employs nested arrangements where contact plugs are positioned within openings through insulating layers, and interconnection layers are stacked one above another with each layer nested within the vertical profile of the structure below. This nesting allows multiple interconnection levels to occupy minimal horizontal space, reducing chip area while supporting increased integration.
4Productivity
If the number of word lines stacked is increased, then the degree of integration is improved, but the process difficulty for contact formation increases
Solution Approach 1:
The contact formation process is segmented into discrete steps for each word line level: forming first contact plugs for first and second word lines, then forming second contact plugs for third and fourth word lines. Each contact plug formation is performed independently through its own opening in the insulating layer, allowing standardized repetitive processes that reduce overall manufacturing difficulty despite the increased number of contacts.
Solution Approach 2:
The insulating layers and openings are prepared in advance before contact plug formation. The tunnel barrier and charge storage layers are pre-formed as stacked structures, and openings are pre-defined at appropriate positions. This preliminary preparation simplifies the subsequent contact formation process by providing ready-made templates and reducing the complexity of aligning multiple contacts simultaneously.
Data Source
AI summary
An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.