Vertical Semiconductor Memory Device Integration Density
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in integration density due to the high cost and complexity of forming fine patterns, which restricts their performance and manufacturing efficiency.
Innovation Solution
A semiconductor memory device with a vertical structure and a body conductive layer that includes a cell array portion and a peripheral circuit portion, featuring a connection conductive pattern that penetrates a residual substrate, allowing for improved electrical characteristics and reduced thickness, thereby increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-dimensional semiconductor memory devices are used, then manufacturing processes are established, but integration density is limited due to the high cost and complexity of forming fine patterns
Solution Approach 1:
The patent transitions from conventional two-dimensional memory cell arrangements to a three-dimensional vertical structure where gate electrodes are stacked vertically. This dimensional change allows integration density to increase without requiring finer lateral patterning, thereby reducing manufacturing complexity while improving integration density
2Manufacturing precision
If the thickness of the semiconductor memory device is reduced, then integration density increases, but electrical characteristics may deteriorate
Solution Approach 1:
By stacking gate electrodes vertically in the third dimension, the device achieves higher integration density without reducing thickness in the lateral plane. This vertical stacking maintains adequate electrical characteristics while increasing the number of memory cells per unit area
Solution Approach 2:
The body conductive layer is divided into a cell array portion and a peripheral circuit portion, with the peripheral circuit portion positioned at a lower level. This segmentation allows independent optimization of electrical characteristics in different regions while maintaining high integration density overall
Data Source
AI summary
A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.