Vertical Memory Devices With Staircase Gate Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the manufacturing of VNAND flash memory devices with a cell-over-peri (COP) structure, the cell array is contaminated by metal components from contact plugs and wirings, and the high temperature process used can deteriorate the characteristics of these metal components.
Innovation Solution
A vertical memory device design featuring gate electrodes with a staircase shape and contact plugs/wirings that gradually increase/decrease in width to prevent contamination and withstand high temperature processes without deterioration, ensuring enhanced electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If contact plugs and wirings are formed before cell array in COP structure, then peripheral circuit can be formed first, but cell array becomes contaminated by metal components and high temperature process deteriorates metal characteristics
Solution Approach 1:
The patent inverts the conventional COP structure by forming the cell array before the peripheral circuit (POC structure). This reversal prevents metal contamination of the cell array during peripheral circuit formation and avoids high-temperature damage to metal components, thereby maintaining electrical characteristics while preserving manufacturing flexibility.
Solution Approach 2:
The cell array is formed in advance before the peripheral circuit and its metal components are introduced. This preliminary formation of the cell array ensures it is not exposed to metal contamination or high-temperature processes that would deteriorate its electrical characteristics.
2Productivity
If high temperature process is used to form cell array, then cell array can be formed effectively, but characteristics of metal contact plugs and wirings are deteriorated
Solution Approach 1:
By inverting the formation sequence to POC structure, the metal components are formed after the cell array is already complete. This allows high-temperature cell array formation without exposing metal components to damaging temperatures, maintaining their electrical characteristics while preserving manufacturing efficiency.
3Ease of manufacture
If contact plugs and wirings are formed early, then manufacturing process can proceed in conventional sequence, but metal components contaminate the cell array
Solution Approach 1:
The patent inverts the conventional sequence to form the cell array before metal components (POC structure). This inversion eliminates metal contamination of the cell array while maintaining straightforward manufacturing processes, thereby achieving both manufacturing simplicity and high cell array purity.
Data Source
AI summary
A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.