Vertical Memory Stress Control via Lattice Mismatch
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Solution Overview
Problem
As the number of stacked layers in three-dimensional semiconductor devices increases, structural distortions such as bending occur due to uncontrolled stress, which affects the integration and stability of the device.
Innovation Solution
The semiconductor device incorporates a stress control mechanism using alternating layers of conductive patterns and insulating structures with different lattice constants, applying compressive and tensile stresses in opposite directions to offset each other, thereby maintaining structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked layers is increased to improve integration, then the degree of integration increases, but structural distortion such as bending occurs due to uncontrolled stress
Solution Approach 1:
The patent applies parameter changes by selecting insulating layers with different lattice constants (e.g., SiO2 with 4.63 Å, Si3N4 with 4.38 Å, SiC with 3.08 Å) to generate controlled stress. By changing the material parameter (lattice constant) of the insulating layers, the patent achieves stress control that prevents structural distortion while maintaining high integration through increased stacked layers
Solution Approach 2:
The patent uses composite materials by stacking multiple insulating layers with different lattice constants between the channel layer and reference layer. This composite structure of alternating insulating layers (e.g., SiO2/Si3N4/SiC combinations) creates balanced stress distribution that maintains structural stability while enabling higher integration
2Stability of the object's composition
If stress control layers are added to maintain structural stability, then structural distortion is reduced, but device complexity increases
Solution Approach 1:
The insulating layers serve multiple functions: they provide electrical insulation between conductive patterns and simultaneously act as stress control layers through their lattice constant differences. This multi-functionality reduces device complexity by combining insulation and stress control into a single component rather than requiring separate stress control layers
Solution Approach 2:
The patent controls stress by changing the lattice constant parameter of insulating layers that are already part of the device structure. By selecting insulating materials with specific lattice constants, the patent achieves stress control without adding extra layers, thereby maintaining structural stability while minimizing increases in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces structural distortions and improves the overall stability of the semiconductor device by controlling stress across layers, enhancing the integration and performance of memory cells.
Implementation Method 1
The first insulating structure may induce a first stress and the second insulating structure may induce a second stress in a direction opposite to the first stress
Implementation Method 2
The stress control insulating layer may include a first material layer arranged closer to the first stacked body than the second stacked body and a second material layer arranged closer to the second stacked body than the first stacked body
Data Source
AI summary
The present disclosure relates to a semiconductor device including a stress control insulating layer or a stress control pattern to control a stress applied to an interlayer insulating layer or a stacked body in a desirable direction.