Vertical Memory Channel Density via Subchannel Division
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Solution Overview
Problem
As the number of steps in VNAND flash memory devices increases, it becomes difficult to form channel holes due to high aspect ratios, and increasing channel hole widths leads to increased device area, making it challenging to maintain channel density without failing due to aspect ratio increases.
Innovation Solution
A vertical memory device design that includes a mold structure with gate electrodes and insulation patterns at multiple levels, where channel holes are divided into subchannels by a division pattern, allowing for increased channel density without expanding the device area, and featuring gate electrodes that include ground selection, word, and string selection lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of steps vertically stacked in VNAND flash memory device increases, then storage capacity is improved, but it becomes more difficult to form channel holes due to high aspect ratio
Solution Approach 1:
The patent divides each channel hole into multiple subchannels using division patterns that extend through the channel hole in the vertical direction. This segmentation allows the channel hole to be formed with a smaller effective width while still providing sufficient conduction paths, thereby reducing the aspect ratio difficulty while maintaining storage capacity through increased vertical stacking.
2Ease of manufacture
If the widths of the channel holes are increased, then ease of forming channel holes is improved, but the area of the VNAND flash memory device increases
Solution Approach 1:
The patent transitions from horizontal channel hole expansion to vertical subchannel division. Instead of increasing channel hole width in the horizontal plane, the invention creates multiple subchannels within the vertical dimension of each channel hole, allowing efficient use of horizontal space while maintaining manufacturability through controlled channel hole dimensions.
3Quantity of substance
If channel holes are divided into subchannels, then channel density is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functional components into integrated structures: the division pattern is formed within the channel hole filling process, the gate electrodes are positioned to control multiple subchannels simultaneously, and the insulation patterns are incorporated during the same fabrication sequence. This merging approach increases channel density while minimizing the addition of separate structural elements that would increase complexity.
Data Source
AI summary
A vertical memory device includes a mold structure and channels. The mold structure includes gate electrodes and insulation patterns arranged on a substrate in which the gate electrodes are disposed at a plurality of levels, respectively, in a vertical direction substantially perpendicular to an upper surface of the substrate. The insulation patterns are disposed between neighboring ones of the gate electrodes. The channels extend through the mold structure in the vertical direction in a hole, and are spaced apart from each other in a horizontal direction substantially parallel to the upper surface of the substrate in the hole. The gate electrodes each includes a plurality of first gate electrodes spaced apart from each other substantially horizontally. The hole extends through one of the first gate electrodes included in each of the gate electrodes. A plurality of channels may be formed in the one hole in the one first gate electrode.