Vertical Transistor Memory Layout for Simpler Word-Line Routing
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Solution Overview
Problem
Planar memory cells face density limitations and complex interconnection challenges as feature sizes approach a lower limit, making manufacturing costly and difficult.
Innovation Solution
A memory device with vertical transistors is implemented, where at least part of the transistor is disposed in a substrate, reducing the occupied area and simplifying the connection structure between the transistor and the word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to a vertical (3D) architecture where memory cells are stacked above the substrate. This dimensional change allows continued scaling and density improvement without proportionally increasing manufacturing complexity, as the vertical stacking approach simplifies certain interconnection requirements compared to further scaling planar cells.
2Quantity of substance
If feature sizes of memory cells approach a lower limit, then memory density is improved, but planar process and fabrication techniques become challenging and costly
Solution Approach 1:
By moving to vertical memory cell structures stacked above the substrate, the patent avoids the fabrication challenges associated with further scaling planar feature sizes. The vertical architecture maintains larger lateral dimensions while achieving high density through the third dimension, thereby improving ease of manufacture.
3Quantity of substance
If the dimension of the memory device becomes smaller and memory cell density becomes higher, then memory density is improved, but the interconnection structure between memory array and peripheral devices becomes more complicated
Solution Approach 1:
The vertical memory array architecture positions memory cells above the substrate, allowing peripheral devices to be placed on the same substrate level. This spatial arrangement simplifies interconnection structures by reducing the need for complex through-substrate vias and multi-layer routing that would be required in highly dense planar configurations.
Solution Approach 2:
The patent integrates the memory array and peripheral devices on the same substrate, merging previously separate components (memory array on one substrate, peripheral devices on another) into a unified structure. This integration reduces interconnection complexity by eliminating the need for complex inter-substrate bonding and routing.
Data Source
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AI summary
A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in a vertical direction. The first vertical transistor is electrically connected with the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.