Vertical MESFET Access Structure for 3D Multi-State Memory
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Solution Overview
Problem
Current stackable 3D memory access devices, such as Ovonic threshold switches and recrystallized Si diodes, face challenges including snap-back behavior, material limitations, sensitivity to reactive ion etching, and device non-uniformity, which hinder their ability to provide multi-state memory functionality and high bit density.
Innovation Solution
The development of a back-end-of-line (BEOL) compatible vertical metal-semiconductor field-effect transistor (MESFET) device with a crystallized silicon layer, formed through laser annealing and multiple electrode layers, offering bi-directional access and improved current control, enabling 3D stackability and compatibility with both Phase Change Memory (PCM) and Resistive Random Access Memory (RRAM) technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If Ovonic threshold switches are used as access devices, then device simplicity is maintained, but snap-back behavior occurs and multi-state memory functionality is hindered
Solution Approach 1:
The access device is segmented into multiple functional regions within the semiconductor layer, including a first region with first dopant concentration and a second region with second dopant concentration. This segmentation allows different regions to perform different functions, enabling multi-state memory functionality while maintaining device simplicity through a single-layer structure.
Solution Approach 2:
Different regions of the semiconductor layer are doped with different dopant concentrations to create local variations in electrical properties. The first region has a first dopant concentration optimized for one function, while the second region has a second dopant concentration optimized for another function, allowing the device to achieve multi-state memory functionality through localized property variations.
2Ease of manufacture
If recrystallized Si diodes are used as access devices, then manufacturing process is simplified, but device non-uniformity and sensitivity to reactive ion etching increase
Solution Approach 1:
The semiconductor layer is doped with different dopant concentrations during the formation process, before any etching or further processing occurs. This preliminary doping action ensures that the desired electrical properties are established early, reducing sensitivity to subsequent reactive ion etching processes and minimizing device non-uniformity.
Solution Approach 2:
The dopant concentration parameter is varied across different regions of the semiconductor layer, with the first region having a first dopant concentration and the second region having a second dopant concentration. This parameter change allows optimization of electrical properties for multi-state memory functionality while maintaining manufacturing simplicity.
3Reliability
If vertical MESFET device with crystallized silicon layer is implemented, then current control and bit density are improved, but device structure and manufacturing process become more complex
Solution Approach 1:
The patent transitions from planar device structures to a vertical MESFET configuration with a crystallized silicon layer grown in the vertical direction. This dimensional change allows for better current control through the vertical channel structure while enabling 3D stacking for increased bit density, as the vertical orientation facilitates layer-by-layer stacking of memory cells.
Solution Approach 2:
The device employs a composite structure combining metal electrodes, oxide layers, and a crystallized silicon layer with specific dopant concentrations. This composite material approach enables superior current control characteristics by leveraging the complementary properties of different materials, while the vertical integration maintains manufacturing feasibility through established semiconductor processing techniques.
4Quantity of substance
If 3D stackable memory array is implemented, then bit density is increased, but access device performance and manufacturing compatibility must be maintained
Solution Approach 1:
The memory array is organized in a three-dimensional stacked configuration with multiple memory cells stacked vertically. The vertical MESFET access devices are oriented to control current flow through the vertical channel, enabling independent addressing and control of each stacked memory cell. This 3D architecture increases bit density while maintaining access device performance through the vertical field effect transistor mechanism.
Solution Approach 2:
The vertical MESFET access device structure is designed to be universal and compatible with both Phase Change Memory (PCM) and Resistive Random Access Memory (RRAM) technologies. The same access device architecture can control current flow through different memory material stacks, enabling a single platform to support multiple memory technologies and achieving high bit density through 3D stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances bit density and facilitates multi-state memory functionality by providing better control over current levels and compatibility with existing BEOL processes, addressing the limitations of previous access devices.
Implementation Method 1
forming a crystallized silicon layer on the first electrode, wherein forming the crystallized silicon layer includes laser annealing the crystallized silicon layer
Data Source
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AI summary
A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.