Vertical MOSFET Selection Transistor for Leakage Suppression
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Solution Overview
Problem
As memory cell sizes shrink, the leakage current of conventional planar MOSFET selection transistors increases, leading to sneak path leakage and false readings, while maintaining a large selection transistor size is necessary to prevent leakage, which limits the miniaturization of memory cells.
Innovation Solution
Implementing a vertical MOSFET selection transistor with a semiconductor body having trenches that form a raised structure with vertically extending gate electrodes, reducing the surface area and size of the selection transistor without increasing leakage, allowing for smaller memory cell dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of selection transistor is reduced to enable memory cell miniaturization, then memory cell density increases, but leakage current increases causing sneak path leakage and false readings
Solution Approach 1:
The patent transitions from a planar (2D) selection transistor design to a vertical (3D) design where the channel extends in the vertical dimension through trenches. This dimensional change allows the transistor to maintain adequate channel length for leakage suppression while occupying less lateral area, enabling memory cell miniaturization without sacrificing reliability.
Solution Approach 2:
The selection transistor channel is nested within trenches that extend into the substrate, with gate electrodes positioned within these trenches. This nested structure allows the channel to be confined in a compact vertical space while maintaining sufficient length, achieving both small footprint and effective leakage suppression.
2Reliability
If the size of selection transistor is increased to prevent leakage current, then leakage suppression improves, but memory cell area increases limiting miniaturization
Solution Approach 1:
By moving the channel length extension into the vertical dimension through trenches, the design achieves long channel length (for leakage suppression) without proportional increase in lateral area. The vertical orientation decouples the relationship between channel length and device footprint.
Solution Approach 2:
The channel is segmented into sections within separate trenches, with gate electrodes positioned in these segmented regions. This segmentation allows the total channel length to be distributed across multiple vertical segments, achieving long effective channel length while maintaining compact lateral dimensions.
Data Source
AI summary
Some embodiments of the present disclosure relate to a vertical MOSFET selection transistor that is configured to suppress leakage voltage in the memory cell without limiting the size of the memory cell. The memory selection transistor has a semiconductor body with first and second trenches that define a raised semiconductor structure having a source region, a channel region, and a drain region. A gate structure has a first gate electrode in the first trench, which extends vertically along a first side of the raised semiconductor structure, and a second gate electrode in the second trench, which extends vertically along an opposite, second side of the raised semiconductor structure. The first and second gate electrodes collectively control the flow of current between the source and drain region in the raised semiconductor structure. An electrical contact couples the drain region to a data storage element configured to store data.