Vertical NAND Charge Trap Layer for Better Charge Retention
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Solution Overview
Problem
Charge transfer between memory cells in vertical NAND flash memory devices deteriorates charge retention due to increased stacking and reduced cell height, leading to performance issues.
Innovation Solution
Incorporation of a charge trap layer with fluorite-, perovskite-, or wurtzite-based materials, including nanocrystals with anti-ferroelectric or ferroelectric properties, to enhance charge retention and reduce program and erase voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory cells is increased and cell height is decreased to achieve higher integration, then storage capacity is improved, but charge retention deteriorates due to charge transfer between memory cells
Solution Approach 1:
The patent introduces a charge trap layer as an intermediary component between the channel layer and blocking insulating layer. This charge trap layer captures and holds charges that would otherwise transfer between stacked memory cells, thereby preventing charge leakage and maintaining charge retention in high-density vertical NAND flash memory structures
Solution Approach 2:
The patent employs composite materials in the charge trap layer, combining dielectric materials (such as HfO2, ZrO2, or SiO2) with charge trap materials (such as TiN, TaN, or AlN nanocrystals). This composite structure provides both the electrical isolation needed to prevent charge transfer and the charge trapping capability to maintain data retention in vertically stacked memory cells
2Ease of manufacture
If conventional charge trap materials are used, then manufacturing is simplified, but charge retention and data storage reliability are insufficient in vertical NAND structures
Solution Approach 1:
The patent uses composite materials in the charge trap layer, combining dielectric materials (such as HfO2, ZrO2, or SiO2) with charge trap materials (such as TiN, TaN, or AlN nanocrystals). This composite structure provides both the electrical isolation needed to prevent charge transfer and the charge trapping capability to maintain data retention in vertically stacked memory cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves charge retention and data integrity by lowering program and erase voltages, while minimizing charge transfer between cells, thus enhancing the memory device's performance.
Implementation Method 1
the charge trap layer including a matrix comprising a dielectric and a charge trap material in the matrix and including anti-ferroelectric nanocrystals or ferroelectric nanocrystals
Implementation Method 2
the charge trap layer including a matrix comprising a dielectric and a charge trap material in the matrix and including anti-ferroelectric nanocrystals or ferroelectric nanocrystals
Implementation Method 3
the charge trap layer including a matrix comprising a dielectric and a charge trap material in the matrix
Data Source
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AI summary
A vertical NAND flash memory device includes a plurality of cell arrays (110), where each cell array of the plurality of cell arrays includes a channel layer (129), a charge trap layer (125) provided on the channel layer, the charge trap layer including a matrix comprising a dielectric (125a) and a charge trap material (125b) in the matrix and including anti-ferroelectric nanocrystals (126) or ferroelectric nanocrystals (126), and a plurality of gate electrodes (121) provided on the charge trap layer.