Vertical NAND Mid-String Devices for Erase Voltage Propagation
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Solution Overview
Problem
Traditional flash memory devices with vertically stacked NAND architecture face challenges in efficiently erasing memory cells due to their isolation from the substrate, requiring alternative approaches for programming and erasing operations.
Innovation Solution
The implementation of a vertical NAND memory architecture where mid-string devices are used to propagate erase voltage to memory cell stacks, allowing for efficient erasure and programming by controlling the substrate and mid-string devices to form a single NAND string for read and programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase bit density, then storage capacity is improved, but erasure operation becomes difficult due to substrate isolation
Solution Approach 1:
The patent divides the memory structure into multiple independent NAND strings, each with its own substrate connection path. This segmentation allows erase voltage to be applied to specific strings without affecting others, solving the erasure difficulty caused by vertical stacking isolation.
Solution Approach 2:
The patent introduces mid-string devices as intermediary elements between the substrate and vertically stacked memory cells. These mid-string devices provide a conductive path for erase voltage propagation, acting as mediators that connect the substrate to isolated vertical cells and enable efficient erasure operations.
2Productivity
If mid-string devices are used to propagate erase voltage, then erasure efficiency is improved, but device complexity increases
Solution Approach 1:
The mid-string devices are designed to perform multiple functions: they serve as select gates for read/program operations and as voltage propagation paths for erasure operations. This multi-functionality reduces the need for separate dedicated erase structures, thereby limiting the increase in device complexity while maintaining high erasure efficiency.
3Area of stationary object
If vertically stacked architecture is implemented, then area utilization is improved, but operational efficiency deteriorates
Solution Approach 1:
The patent implements dynamic control of mid-string devices that can be selectively activated or deactivated based on the operation type (read, program, or erase). This dynamic switching capability allows the vertically stacked architecture to maintain high area utilization while achieving operational efficiency comparable to planar structures through adaptive voltage distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high bit density and efficient erasure and programming of vertically stacked memory cells, addressing the challenge of substrate isolation and improving operational efficiency in flash memory devices.
Implementation Method 1
mid-string devices are controlled to allow the substrate to couple to the first and second bodies
Implementation Method 2
an erase voltage is applied to the substrate. The erase voltage may then propagate through the one or more mid-string devices to the first and second bodies
Data Source
AI summary
A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND memory cells to the substrate for erase operations. In the second mode, the one or more mid-string devices couple the body of a first stack of NAND memory cells to a body of a second stack of memory NAND memory cells, allowing the two stacks operate as a single NAND string for read and programming operations.