Vertical NAND Memory Fabrication via Planar Trench Inversion
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Solution Overview
Problem
Conventional NAND architecture fabrication processes face difficulties with high aspect ratio contacts, such as pillars, which complicate the formation of channel regions and lead to inefficiencies in semiconductor construction.
Innovation Solution
The fabrication of substantially vertical NAND strings using line and space patterns for channel and isolation regions, avoiding the challenges of high aspect ratio contacts by forming memory cell stacks with alternating control gate and dielectric materials, and utilizing etching and deposition processes to create specific trench and cavity structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional NAND architecture uses high aspect ratio contacts (pillars) to form channel regions, then vertical integration is achieved, but the fabrication process becomes complicated and less efficient
Solution Approach 1:
The patent inverts the conventional approach by forming channel regions through planar trenches instead of vertical pillars. The channel regions are created by removing sacrificial material from trenches, reversing the traditional high-aspect-ratio contact methodology and simplifying the fabrication process while maintaining vertical integration capability
Solution Approach 2:
The patent extracts the channel region formation from the complex pillar-based process by using separate trenches for channel regions. This separates the channel formation step from the vertical stack formation, eliminating the need for high aspect ratio contacts and reducing overall fabrication complexity
2Shape
If conventional NAND architecture uses pillars to support channel regions, then vertical structure is achieved, but manufacturing efficiency decreases
Solution Approach 1:
The patent inverts the support structure approach by using planar trenches with sacrificial material instead of vertical pillars. The channel regions are formed by removing sacrificial material from trenches, creating vertical structures through a planar process that is more manufacturable and efficient
Solution Approach 2:
The patent applies preliminary action by depositing sacrificial material into trenches before forming the final channel regions. This pre-positioning of sacrificial material simplifies subsequent processing steps and improves manufacturing efficiency by enabling parallel fabrication of multiple structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the development of improved NAND architectures and methods for semiconductor construction, enhancing the efficiency and reliability of memory cell formation, applicable to various memory types like NAND and NOR.
Implementation Method 1
utilizing etching and deposition processes to create specific trench and cavity structures
Implementation Method 2
utilizing etching and deposition processes to create specific trench and cavity structures
Data Source
AI summary
Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions.