Vertical Nonvolatile Memory Integration Density
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Solution Overview
Problem
The integration density of two-dimensional or planar semiconductor memory devices is limited by the cost of equipment for forming small feature sizes, which hinders the increase in integration density and subsequently affects the performance and pricing of semiconductor devices.
Innovation Solution
A nonvolatile memory device with a vertical structure is developed, featuring inter-gate insulating patterns, gate electrodes, a vertical active pillar, a charge-storing layer, a tunnel insulating layer, and a blocking insulating layer, where the charge-storing layer includes silicon nitride and silicon oxynitride layers, and the tunnel and blocking insulating layers are optimized with specific nitrogen concentrations to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar memory devices are used, then manufacturing process is simpler, but integration density is limited due to equipment cost for forming small feature sizes
Solution Approach 1:
The patent transitions from two-dimensional planar memory devices to three-dimensional vertical memory devices. The vertical active pillar structure extends the memory cell into the third dimension (depth), allowing multiple memory cells to be stacked vertically. This dimensional change enables higher integration density without requiring smaller feature sizes, thus avoiding the need for expensive lithography equipment while achieving increased capacity.
2Quantity of substance
If feature size is decreased to increase integration density, then integration density improves, but equipment cost increases significantly
Solution Approach 1:
Instead of decreasing feature size in the planar direction, the patent increases integration density by extending the structure vertically. The vertical active pillar and stacked gate electrodes utilize the third dimension to pack more memory cells into the same footprint area, achieving higher integration density without requiring advanced (and expensive) lithography tools for smaller features.
Solution Approach 2:
The patent changes the structural parameters from planar dimensions to vertical dimensions. By forming vertical active pillars with specific heights and stacking gate electrodes at different heights, the design achieves higher integration density through parameter optimization in the vertical direction rather than reducing lateral feature sizes, thereby avoiding expensive equipment requirements.
3Reliability
If charge-storing layer composition is optimized with nitrogen concentration, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies different nitrogen concentrations to different regions of the charge-storing layer. The first charge-storing layer (silicon nitride) has a higher nitrogen concentration than the second charge-storing layer (silicon oxynitride). This local quality variation optimizes electron trapping and retention characteristics in different regions, improving overall device reliability while using a manageable multi-layer structure.
Solution Approach 2:
The charge-storing layer is constructed as a composite structure with two distinct materials: silicon nitride and silicon oxynitride. Each material contributes different properties - silicon nitride provides high nitrogen content for electron trapping, while silicon oxynitride provides a gradient transition. This composite approach enhances reliability by combining the advantages of different materials in a systematic multi-layer configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution improves the reliability and operational characteristics of nonvolatile memory devices by increasing integration density, reducing de-trapping of electrons, and maintaining a higher threshold voltage margin between program states, thus addressing the limitations of traditional two-dimensional devices.
Implementation Method 1
a tunnel insulating layer between the charge-storing layer and the vertical active pillar
Implementation Method 2
the charge-storing layer may include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively, the first charge-storing layer may be a silicon nitride layer, and the second charge-storing layer may be a silicon oxynitride layer
Data Source
AI summary
A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.