Vertical Non-Volatile Memory Device Amorphous Oxynitride Charge Trap
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in preventing charge diffusion or leakage between cells, which limits their capacity and efficiency.
Innovation Solution
The implementation of a vertical non-volatile memory device structure incorporating a charge trap layer with amorphous oxynitride, a charge blocking layer, and specific material compositions to reduce charge leakage, including a charge tunneling layer and channel layer, along with a pillar and gate electrodes, enhances charge storage efficiency and reduces diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cell structures are used, then device simplicity is maintained, but charge diffusion or leakage between cells occurs
Solution Approach 1:
The memory cell is divided into multiple functional layers including charge tunneling layer, charge trap layer, and charge blocking layer, each performing a specific function to prevent charge diffusion while maintaining overall device simplicity
Solution Approach 2:
The charge trap layer is surrounded by charge tunneling layer and charge blocking layer in a nested configuration, creating concentric functional zones that efficiently contain charges within the memory cell
2Reliability
If charge trap layer with amorphous oxynitride is implemented, then charge diffusion is reduced, but manufacturing complexity increases
Solution Approach 1:
The charge trap layer uses amorphous oxynitride with specific compositional parameters (x≥0.3, 0<y≤0.5, 0≤z≤0.7, x+y+z≤1.0) to achieve optimal charge isolation properties while maintaining manufacturability through controlled deposition processes
Solution Approach 2:
The charge trap layer is formed as a composite amorphous oxynitride material combining oxygen and nitrogen in specific ratios to create a structure that simultaneously provides charge trapping capability and resistance to charge diffusion
3Reliability
If multiple layers are added to prevent charge leakage, then charge storage efficiency improves, but device complexity increases
Solution Approach 1:
The patent transitions from planar memory cell architecture to vertical stacking of functional layers (tunneling, trapping, blocking layers) to achieve improved charge storage efficiency while maintaining a compact footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces charge diffusion between cells, increasing the memory device's capacity and efficiency while maintaining thermal stability and low power consumption.
Implementation Method 1
a charge trap layer surrounding a side surface of the charge tunneling layer and including an amorphous oxynitride
Implementation Method 2
a charge tunneling layer surrounding a side surface of the channel layer
Data Source
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AI summary
A vertical non-volatile memory device and an electronic apparatus including the vertical non-volatile memory device are provided. The vertical non-volatile memory device includes a pillar, a channel layer surrounding a side surface of the pillar, a charge tunneling layer surrounding a side surface of the channel layer, a charge trap layer surrounding a side surface of the charge tunneling layer and including an amorphous oxynitride, a charge blocking layer surrounding a side surface of the charge trap layer, and a plurality of separation layers and a plurality of gate electrodes surrounding a side surface of the charge blocking layer and alternately arranged along the side surface of the charge blocking layer.