Vertical Non-Volatile Memory Integration Density
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Solution Overview
Problem
Current non-volatile memory devices face challenges in increasing integration density and reliability due to their planar transistor structures, which limit their capacity and performance in smaller electronic products.
Innovation Solution
A non-volatile memory device with a vertical structure is developed, featuring a semiconductor layer pattern with alternately stacked gate and interlayer insulating layers, a storage structure including a tunnel insulating layer, charge storage layer, and blocking insulating layer, and a method of manufacturing that involves etching sacrificial layers and forming gate patterns with recessed barrier and conductive layers to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar transistor structure is used, then the device structure is simple and easy to manufacture, but the integration density is limited
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a vertical three-dimensional structure. The semiconductor layer extends vertically from the substrate, with gate patterns wrapped around the side walls, enabling higher integration density by utilizing the vertical dimension for stacking multiple memory cells and components.
Solution Approach 2:
The gate patterns are nested around the semiconductor layer in a wrap-around configuration. The first gate pattern is positioned at a first level wrapping around the semiconductor layer, while the second gate pattern is at a second level also wrapping around, creating a nested multi-layer structure that increases functional density within the vertical space.
2Productivity
If the gate patterns are extended to the side wall of the interlayer insulating layer patterns, then the transistor coverage is maximized, but the tunnel insulating layer durability is compromised
Solution Approach 1:
The patent applies different spatial configurations to different regions of the gate patterns. The first gate pattern extends to contact the side wall of the interlayer insulating layer pattern at the first level, while the second gate pattern is positioned at a second level and does not extend to contact the side wall. This local differentiation allows optimized transistor coverage in the first region while preserving tunnel insulating layer durability in the second region.
Data Source
AI summary
According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.