Vertical Oxide Semiconductor Memory Cell for Low-Leakage Retention
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing area, power consumption, and maintaining data retention after power loss, particularly in volatile and non-volatile memory devices.
Innovation Solution
A semiconductor device structure incorporating a first transistor, a second transistor, and a capacitor, where the second transistor and capacitor are stacked over the first transistor, utilizing a wide band gap oxide semiconductor for reduced off-state current, and sharing manufacturing processes to minimize area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a DRAM is used to achieve small area, then area is reduced, but data retention period becomes extremely short and power consumption cannot be sufficiently reduced
Solution Approach 1:
The patent combines the transistor and capacitor into a single integrated memory element structure where the transistor's gate electrode serves as one electrode of the capacitor, and the insulating film between source and drain regions serves as the capacitor's dielectric layer. This merging allows the memory element to retain charge longer while maintaining small area.
Solution Approach 2:
The patent changes the electrical parameters of the transistor by using an oxide semiconductor material with wide band gap, which provides high off-state resistance and enables long data retention periods without requiring large capacitors, thus maintaining small area while improving retention.
2Speed
If an SRAM is used to operate at high speed, then speed is improved, but area becomes large and power consumption during data retention cannot be sufficiently reduced
Solution Approach 1:
The patent merges the transistor and capacitor functions into a single integrated element, eliminating the need for separate components required in SRAM structures. This integration reduces the overall area while maintaining high-speed operation capability through the optimized transistor design.
3Duration of action of stationary object
If a flash memory is used to hold electric charge in floating gate for semi-permanent retention, then data retention is improved, but power consumption increases due to high voltage requirements and insulating film degradation
Solution Approach 1:
The patent changes the material parameter by using oxide semiconductor with wide band gap, which enables the transistor to maintain high off-state resistance at low voltages. This eliminates the need for high voltage operations required by flash memory, significantly reducing power consumption while maintaining long data retention.
Solution Approach 2:
The patent uses a thin oxide semiconductor film as the insulating layer, which can be easily formed through conventional semiconductor processing. This thin film provides sufficient insulation without requiring the thick, degradation-prone insulating films needed in flash memory, reducing both power consumption and improving reliability.
4Area of stationary object
If transistor area is reduced through miniaturization, then integration density is improved, but off-state current increases and power consumption during data retention cannot be sufficiently reduced
Solution Approach 1:
The patent changes the material parameter from conventional silicon to oxide semiconductor, which has inherently higher off-state resistance. This material substitution allows the transistor to maintain small area while significantly reducing off-state current and power consumption during data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves reduced area, low power operation, and long-term data retention even after power shutdown, enabling high integration and cost-effective manufacturing.
Implementation Method 1
a transistor formed using an oxide semiconductor with a wide band gap has significantly high off-state resistance
Implementation Method 2
it has been proposed that the transistor is used to form a memory element... owing to the high off-state resistance of the transistor
Implementation Method 3
one memory element of the DRAM includes only one transistor and one capacitor... data is written by accumulating electric charge in the capacitor
Implementation Method 4
a transistor formed using an oxide semiconductor... has significantly high off-state resistance
Data Source
AI summary
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.