Vertical Semiconductor Pillar DRAM Without Capacitors
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Solution Overview
Problem
The miniaturization of dynamic random access memory (DRAM) capacitors is hindered by complex manufacturing processes and high power consumption due to the need for re-writing after reading operations, and the two-transistor capacitor-less (2T0C) DRAM structure faces structural challenges.
Innovation Solution
A semiconductor structure is designed with a semiconductor pillar and gate pillar perpendicular to the substrate, surrounded by a first word line and a semiconductor layer, reducing transistor area and eliminating the need for capacitors, thus simplifying the process and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM capacitor miniaturization is pursued, then storage density is improved, but manufacturing complexity and power consumption increase due to re-writing requirements
Solution Approach 1:
The invention extracts and eliminates the capacitor component from the conventional 1T1C DRAM structure, transitioning to a 2T0C capacitor-less architecture. This removal of the capacitor simplifies the manufacturing process while maintaining storage functionality through a different mechanism (charge trapping in the gate electrode), directly resolving the contradiction between storage density and manufacturing complexity
Solution Approach 2:
The patent employs three-dimensional vertical stacking of transistor structures (multiple tiers stacked above each other) to achieve high storage density without increasing planar footprint. This vertical dimensionality change allows dense integration while using simplified capacitor-less transistor structures, simultaneously improving storage density and reducing manufacturing complexity
2Quantity of substance
If conventional DRAM capacitor miniaturization is pursued, then storage density is improved, but power consumption increases due to re-writing after reading operations
Solution Approach 1:
By removing the capacitor and its associated charge transfer/re-writing mechanisms, the invention eliminates the primary source of power consumption in conventional DRAM. The capacitor-less structure using charge trapping in gate electrodes maintains data retention without requiring periodic refresh operations, thus resolving the contradiction between storage density and power consumption
3Quantity of substance
If transistor size is reduced for higher integration, then integration density is improved, but leakage current increases
Solution Approach 1:
The patent employs oxide semiconductor materials (such as IGZO - indium gallium zinc oxide) for the transistor channel region, which exhibit superior electrical characteristics with extremely low off-state leakage current. This composite material approach enables high integration density while maintaining low leakage current, directly resolving the contradiction between integration density and leakage current
Solution Approach 2:
The invention changes the material parameter (using oxide semiconductors with wide bandgap) to fundamentally alter the electrical characteristics of the transistor, achieving low leakage current even at scaled dimensions. This parameter change enables continued scaling for higher integration without the leakage penalties typically associated with smaller transistors
Data Source
AI summary
Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate; a semiconductor pillar located on the substrate and a gate pillar located on the semiconductor pillar, in which the semiconductor pillar and the gate pillar both extend in a direction perpendicular to a plane of the substrate; a first word line extending in a first direction parallel to the plane of the substrate and surrounding the semiconductor pillar; and a semiconductor layer located above the semiconductor pillar and at least surrounding a sidewall of the gate pillar.