Vertical Semiconductor Pillar with Mesa-Extended Bit Line
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Solution Overview
Problem
Manufacturing vertical type semiconductor devices with high performance and high reliability is challenging due to their complex manufacturing process, which hinders the development of smaller, more integrated integrated circuit devices for electronic products.
Innovation Solution
The design includes a vertical type integrated circuit device with a substrate and a pillar structure featuring a lower impurity region, a vertical channel region, and an upper impurity region, along with conductive lines and a gate insulating layer, allowing for a compact and reliable semiconductor device structure. This structure includes a bit line and word line arrangement that facilitates efficient current flow and reduces resistance, enabling high performance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical type semiconductor device is manufactured, then integration density and data storage capacity are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent transitions from conventional planar transistor structures to vertical channel structures, utilizing the third dimension (vertical direction) to increase integration density. The vertical channel extends from the substrate surface downward, allowing multiple devices to be packed in a smaller footprint area while maintaining effective channel length for transistor operation.
Solution Approach 2:
The patent implements a nested structure where the vertical channel is surrounded by a gate electrode, which is in turn surrounded by insulating layers and conductive lines. The gate insulating layer wraps around the vertical channel, and the bit line and word line are positioned in nested relationships to achieve three-dimensional integration without excessive manufacturing complexity.
2Area of moving object
If vertical channel structure is used, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning steps where insulating layers and conductive lines are formed with predetermined patterns before the final vertical channel formation. The gate insulating layer is deposited and patterned in advance to define the vertical channel region, ensuring precise alignment without requiring extremely tight final alignment tolerances.
Solution Approach 2:
The patent uses asymmetric positioning of the bit line and word line relative to the vertical channel structure. The bit line is positioned at a first location while the word line is positioned at a second location, creating an asymmetric layout that simplifies the alignment process compared to symmetric configurations that would require precise centering from multiple directions.
3Productivity
If conductive lines are positioned close to the vertical channel, then device integration is improved, but electrical interference increases
Solution Approach 1:
The patent introduces a gate insulating layer as an intermediary between the vertical channel and the surrounding conductive lines (bit line and word line). This insulating layer acts as a mediator that allows the conductive lines to be positioned close to the vertical channel for high integration while preventing direct electrical contact and reducing interference through electrical isolation.
Solution Approach 2:
The patent applies different material properties to different regions: the gate insulating layer provides electrical isolation where conductive lines are close to the channel, while other regions use conductive materials for signal transmission. This local differentiation of material quality allows close proximity integration without suffering from electrical interference in critical regions.
Data Source
AI summary
A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.