Vertical PIN Structure for High Breakdown Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with PIN structures for high withstand voltage performance occupy large areas, limiting their suitability for microfabrication and increasing chip size, especially when used in input/output sections of semiconductor devices.
Innovation Solution
A semiconductor device is designed with a PIN structure formed in the stacking direction, comprising a first conductivity-type layer, an intermediate layer with low or no impurity concentration, and a second conductivity-type layer, which reduces the planar area occupancy and allows for higher breakdown voltage while maintaining efficient impurity distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PIN structure is formed in an in-plane direction of a semiconductor substrate, then the breakdown voltage is improved, but the occupancy area increases
Solution Approach 1:
The patent transitions the PIN structure from in-plane formation to vertical stacking in the thickness direction. This dimensional change allows the depletion layer to extend vertically through the intermediate layer, maintaining the required breakdown voltage while significantly reducing the planar occupancy area. The first conductivity-type layer, intermediate layer, and second conductivity-type layer are stacked vertically to form the PIN junction, enabling high voltage withstand capability in a compact footprint suitable for microfabrication.
2Reliability
If the width of the depletion layer is increased to achieve higher breakdown voltage, then the withstand voltage performance is improved, but the occupancy area increases
Solution Approach 1:
Instead of increasing the depletion layer width in the planar direction, the patent extends the depletion layer vertically through the thickness direction by stacking layers. The intermediate layer with low impurity concentration enables the depletion region to penetrate vertically, achieving the necessary breakdown voltage without expanding the device footprint.
Solution Approach 2:
The patent modifies the impurity concentration parameter in the intermediate layer, setting it to be lower than in the adjacent conductivity-type layers. This parameter change enables broader depletion layer formation vertically while maintaining a compact planar structure, thus achieving high breakdown voltage without increased occupancy area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables semiconductor devices to withstand higher voltages with a more efficient occupancy area, addressing the challenge of large area occupancy in traditional PIN structures and facilitating smaller chip sizes.
Implementation Method 1
a depletion layer is formed between the low-dose intermediate layer and each of the P-type semiconductor and the N-type semiconductor; therefore, an electric field between the P-type semiconductor and the N-type semiconductor is relaxed by the formed depletion layer
Data Source
AI summary
A semiconductor device including a first conductivity-type layer into which first conductivity-type impurities are introduced, a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities, and an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate.