Vertical/Planar-Launched MicroLED Links for Chiplet Interconnects
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Solution Overview
Problem
Chip-to-chip connections in integrated circuits require more power and are less dense compared to on-chip connections, limiting the performance and efficiency of chiplet-based systems.
Innovation Solution
Implementing optical chip-to-chip interconnects using microLEDs as light sources, which provide high connection density, low latency, and efficient power consumption through the use of microLEDs and parallel optical links (POLs) with vertically launched and planar launched parallel optical links (VLPOLs and PLPOLs) to connect integrated circuit chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip-to-chip connections are used to connect chiplets, then functionality can be distributed across multiple optimized chiplets, but connection density decreases and power consumption increases
Solution Approach 1:
The patent replaces electrical interconnects with optical interconnects using microLEDs as light sources. This substitution enables chip-to-chip connections to achieve higher density (exceeding 10 Tbps/mm) while reducing power consumption, thereby resolving the contradiction between functionality distribution and connection density.
Solution Approach 2:
The patent changes the fundamental parameter of signal transmission from electrical to optical domain. By using microLEDs modulated at rates exceeding 1 Gbps and implementing both vertically launched and planar launched parallel optical links, the system achieves higher bandwidth and density while maintaining the distributed chiplet architecture.
2Adaptability or versatility
If chip-to-chip connections are used to connect chiplets, then functionality can be distributed across multiple optimized chiplets, but power consumption increases
Solution Approach 1:
The patent replaces electrical interconnects with optical interconnects using microLEDs as light sources. This substitution enables chip-to-chip connections to achieve higher density (exceeding 10 Tbps/mm) while reducing power consumption, thereby resolving the contradiction between functionality distribution and connection density.
3Productivity
If transistor dimensions are shrunk to increase computing performance, then transistor count increases, but marginal performance benefits decrease and costs increase
Solution Approach 1:
The patent divides a monolithic SoC into multiple smaller chiplets that can be independently manufactured and optimized. Each chiplet can be produced with higher yield due to smaller size, and the modular approach allows redistribution of functionality across multiple components, maintaining overall system performance while improving manufacturing reliability.
4Quantity of substance
If a single SoC is used to consolidate functionality, then integration density increases, but the IC process cannot be simultaneously optimized for different functionality
Solution Approach 1:
The patent divides a monolithic SoC into multiple smaller chiplets that can be independently manufactured and optimized. Each chiplet can be produced with higher yield due to smaller size, and the modular approach allows redistribution of functionality across multiple components, maintaining overall system performance while improving manufacturing reliability.
Solution Approach 2:
The patent creates a universal chiplet interconnection platform using optical interconnects that can accommodate various types of chiplets (logic, DRAM, high-speed I/O, etc.). This multi-functional approach allows different chiplet types to be combined in various configurations to meet different application requirements while maintaining a standardized interconnect interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves connection densities of >10 Tbps/mm and <1 Pbps/cm² with low power consumption and latency approaching the speed of light, enhancing the performance and efficiency of high-performance processing and networking applications.
Implementation Method 1
optical chip-to-chip interconnects with microLEDs as light sources
Implementation Method 2
the microLEDs are modulated at rates >1 Gbps
Data Source
AI summary
Integrated circuit chips may be optically interconnected using microLEDs. Some interconnections may be vertically-launched parallel optical links. Some interconnections may be planar-launched parallel optical links.