Vertical PNPN Thyristor DRAM Cell Architecture
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Solution Overview
Problem
Current DRAM memory cell technologies face challenges in scaling below 20 nm design rules, power consumption, and data retention due to the size and complexity of memory cells, particularly with conventional one-transistor one-capacitor cells and alternative architectures like FBDRAM and PNPN thyristor designs.
Innovation Solution
A volatile memory array using vertical PNPN thyristors formed in a bulk silicon substrate, isolated by shallow and deep trenches of insulating material, arranged in a cross-point grid with metal conductors and buried doped layers, allowing for scalable and power-efficient dynamic random access memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional one-transistor one-capacitor DRAM cells are used, then data storage capability is achieved, but memory cell size cannot be reduced further due to scaling limitations below 20 nm
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a vertical 3D thyristor structure. The PNPN thyristor is formed with vertical current flow through doped regions extending into the substrate, enabling compact cell size while maintaining functional integrity through three-dimensional device architecture rather than scaling planar dimensions further.
Solution Approach 2:
The patent changes the fundamental device parameters by replacing the transistor-capacitor architecture with a thyristor-based structure exhibiting negative differential resistance. This parameter change enables new operational modes including bistable states for data storage, allowing smaller cell dimensions while maintaining data retention through the thyristor's inherent latching characteristics.
2Length of moving object
If alternative DRAM architectures like FBDRAM or PNPN thyristor designs are used, then memory cell size can be reduced, but data retention issues or increased complexity arise
Solution Approach 1:
The patent merges the storage and access functions into a single PNPN thyristor device. The thyristor's bistable nature provides data storage capability while its four-terminal structure (anode, cathode, two gates) enables direct access operations, combining multiple functions that would otherwise require separate components into one integrated device.
Solution Approach 2:
The thyristor structure provides self-latching capability through its inherent negative differential resistance characteristic. Once triggered into a conducting state, the device maintains its state without requiring continuous external control signals, enabling data retention through the device's own physical properties rather than requiring additional control circuitry.
3Speed
If lateral PNPN thyristor designs with gates are used, then switching speed is improved, but memory cell area increases substantially
Solution Approach 1:
The patent employs vertical PNPN thyristors with current flow in the vertical dimension rather than lateral current flow. This vertical orientation allows the current path to extend into the substrate depth, achieving fast switching through short lateral current paths while maintaining compact planar cell footprint suitable for high-density memory arrays.
Solution Approach 2:
The patent uses asymmetric doping profiles and unequal base widths in the vertical PNPN structure. The P-N-P-N layers have different thicknesses and doping concentrations optimized for each region, enabling fast switching performance through asymmetric carrier injection and extraction while maintaining vertical current flow that minimizes lateral area requirements.
4Ease of manufacture
If epitaxial or CVD semiconductor layers are added at backend of CMOS process, then PNPN thyristor cells can be formed, but thermal cycles and etching steps degrade performance and yield
Solution Approach 1:
The patent forms the PNPN thyristor structure using dopant implantation into pre-formed CMOS structures before final processing steps. By performing the thyristor formation early in the process sequence using ion implantation rather than backend epitaxial growth, the structure is established before subsequent thermal cycles that could degrade the delicate thyristor characteristics.
Solution Approach 2:
The patent replaces chemical vapor deposition or liquid-phase epitaxial growth with physical ion implantation for forming the thyristor doped regions. This substitution eliminates the need for high-temperature epitaxial processes and associated chemical treatments, using instead a physical doping method that is more compatible with existing CMOS processing and causes less degradation to previously formed structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of smaller, more scalable, and power-efficient DRAM memory cells that maintain data retention with reduced power consumption, addressing the limitations of existing technologies by utilizing a cross-point grid architecture and optimized trench isolation techniques.
Implementation Method 1
Another approach to a new DRAM architecture is based on the negative differential resistance behavior of a PNPN thyristor
Data Source
AI summary
A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.