Vertical PNPN Thyristor DRAM Cell for Sub-20nm Scaling
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Solution Overview
Problem
Current DRAM memory cell designs face challenges in scalability below 20 nm, power consumption, and data retention due to the size of individual memory cells and the complexity of processing techniques, particularly with conventional one-transistor one-capacitor cells and alternative architectures like FBDRAM and PNPN thyristor designs.
Innovation Solution
A volatile memory array using vertical PNPN thyristors formed in a bulk silicon substrate, isolated by shallow and deep trenches of insulating material, arranged in a cross-point grid with metal conductors and buried doped layers, allowing for efficient data storage and reduced power consumption through specific potential applications and sector-based refreshing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional one-transistor one-capacitor DRAM cells are used, then data storage capability is achieved, but memory cell size cannot be reduced further below 20 nm due to manufacturing complexity and charge leakage
Solution Approach 1:
The patent changes the fundamental operating parameters of the memory cell by transitioning from capacitor-based charge storage to thyristor-based resistive state storage. The thyristor utilizes its unique hysteresis characteristic where the device can be switched between high-resistance (off) and low-resistance (on) states, enabling data storage without requiring precise capacitance control or fearing charge leakage, thus allowing further scaling below 20 nm.
Solution Approach 2:
The patent replaces the electrostatic storage mechanism (capacitor) with a solid-state resistive switching mechanism (thyristor). The thyristor's ability to maintain its state through positive feedback between coupled transistors eliminates the need for isolated charge storage, replacing the mechanical/electrostatic system with a field-effect-based system that is more suitable for nanoscale integration.
2Speed
If lateral PNPN thyristor designs with gates are used, then switching speed is improved, but memory cell area increases substantially
Solution Approach 1:
The patent transitions from a lateral (planar) thyristor configuration to a vertical (three-dimensional) configuration. The vertical PNPN thyristor structure allows the current flow path to extend through the thickness of the substrate rather than across the surface, enabling compact integration in the vertical dimension while maintaining the necessary switching characteristics, thus reducing the memory cell footprint significantly.
Solution Approach 2:
The vertical thyristor structure nests multiple doped regions (P-type and N-type layers) within each other in the vertical direction, creating a compact stacked configuration. This nesting approach allows the four-layer PNPN structure to be contained within a small lateral footprint by utilizing the third dimension, effectively packing the thyristor functionality into a minimal area.
3Ease of manufacture
If PNPN thyristors operated in breakdown regime are used, then data writing capability is achieved, but power consumption increases and process control becomes difficult
Solution Approach 1:
The patent changes the operating regime of the thyristor from breakdown mode to hysteresis mode. Instead of utilizing avalanche breakdown or Zener breakdown to switch states, the vertical PNPN thyristor exploits its inherent hysteresis characteristic where the intersection of the load line with the thyristor's I-V curve determines the stable states. This allows data writing through controlled switching at lower voltages, reducing power consumption and simplifying process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a smaller, more scalable DRAM memory cell design that consumes less power and improves data retention by using a cross-point grid architecture with vertical PNPN thyristors, reducing current leakage and requiring less frequent refreshing compared to conventional DRAMs.
Implementation Method 1
Another approach to a new DRAM architecture is based on the negative differential resistance behavior of a PNPN thyristor
Data Source
AI summary
Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.