Vertical Power Delivery IC Stacking for SOC Voltage Consistency
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Solution Overview
Problem
Conventional semiconductor package designs face challenges in efficiently routing power signals and ground signals due to IR drops, leading to voltage inconsistencies across multiple CPUs within a single chip, which affects performance and increases manufacturing costs.
Innovation Solution
A power delivery IC is vertically stacked over a second IC to supply power, utilizing through silicon vias and separate ground and power planes to minimize voltage drops and ensure consistent voltage delivery across electronic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional routing configurations are used for power signals and ground signals, then manufacturing cost increases, but voltage consistency across multiple CPUs is compromised due to IR drops
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical stacking, placing the power delivery IC directly above the CPU die. This dimensional change enables significantly shorter current paths through through-silicon vias, reducing IR drops and improving voltage consistency without increasing manufacturing complexity
Solution Approach 2:
The patent separates the power delivery function into a dedicated power delivery IC, distinct from the CPU die. This segmentation allows each component to be optimized independently and facilitates the vertical stacking architecture that reduces power routing losses
2Reliability
If traces extend from periphery to interior of CPU to supply power, then power can reach interior circuitry, but power is lost along traces due to IR drops
Solution Approach 1:
The patent moves power delivery from a planar trace-based approach to a vertical three-dimensional approach using through-silicon vias. This dramatically shortens the current path length, reducing both the risk of power delivery failures and the energy lost to resistive heating
Solution Approach 2:
The patent introduces a dedicated power delivery IC as an intermediary component between the external power source and the CPU interior circuitry. This intermediary provides regulated and efficient power delivery directly to where it is needed, minimizing losses in the power distribution path
3Adaptability or versatility
If separate power planes and ground planes are used for switch die and CPU die, then each die can be independently powered, but voltage differences due to IR drops prevent CPUs from operating at the same voltage
Solution Approach 1:
The patent uses vertical stacking with through-silicon vias to create a unified power distribution architecture. The power delivery IC above the CPU die provides a common reference voltage to all CPU cores, ensuring voltage uniformity while maintaining the ability to independently power different dies at different voltage levels
Data Source
AI summary
A semiconductor package including i) a first semiconductor die and ii) a second semiconductor die vertically stacked on top of the first semiconductor die. The first semiconductor die includes a first electronic component and a second electronic component, in which the first electronic component operates in accordance with power associated with a first power domain, and the second electronic component operates in accordance with power associated with a second power domain. The second semiconductor die is configured to supply the power associated with the first power domain to the first electronic component of the first semiconductor die, and supply the power associated with the second power domain to the second electronic component of the first semiconductor die.