Vertical Power Device Insulated Groove and Doped Wall
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Solution Overview
Problem
Existing high voltage vertical power components face issues with breakdowns due to the mismatch in thermal expansion between passivation glass and silicon, leading to operational failures under high voltages, and require extensive peripheral structures that increase cost and reduce surface area for electrodes.
Innovation Solution
A vertical power component with a heavily doped P-type diffused wall on the lower face and a deep, insulated annular groove on the upper face, eliminating the need for channel stop regions and reducing the distance between the component edge and electrode limits, while using an oxide layer to prevent surface inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mesa peripheral structure with passivation glass is used, then high voltage breakdown is prevented, but the interface between glass and silicon degrades due to thermal expansion mismatch
Solution Approach 1:
The patent extracts the problematic passivation glass from the peripheral structure and replaces it with an oxide layer formed directly on the silicon substrate. This eliminates the glass-silicon interface that causes thermal expansion mismatch and reliability degradation, while maintaining the necessary electrical isolation and voltage breakdown prevention functions through the oxide layer and heavily doped P-type diffused wall.
Solution Approach 2:
The patent changes the material parameter of the passivation layer from organic passivation glass to inorganic oxide layer, and changes the doping parameter by introducing a heavily doped P-type diffused wall with concentration greater than 10^19 atoms/cm³. These parameter changes eliminate thermal expansion mismatch issues while maintaining high voltage breakdown prevention.
2Reliability
If a heavily doped P-type diffused wall with groove structure is used, then voltage withstand capability is improved, but the distance between component edge and electrode limit increases
Solution Approach 1:
The patent moves the voltage withstand function from a two-dimensional surface structure to a three-dimensional structure by creating a heavily doped P-type diffused wall that extends vertically through the substrate thickness. This vertical dimension allows the electric field to be contained more efficiently, reducing the required horizontal distance between the component edge and electrode limit while maintaining high voltage withstand capability.
3Reliability
If channel stop regions are added to prevent breakdown, then voltage withstand is improved, but the peripheral surface area increases and cost increases
Solution Approach 1:
The heavily doped P-type diffused wall serves multiple functions simultaneously: it acts as a voltage withstand structure, provides electrical isolation, and eliminates the need for separate channel stop regions. This multi-functional design reduces the peripheral surface area and simplifies the manufacturing process while maintaining high voltage withstand capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively withstands voltages over 800 volts without destructive breakdowns, reduces the component's peripheral surface area, and maintains operational integrity by minimizing the interface issues between silicon and passivation materials.
Implementation Method 1
a heavily doped P-type diffused wall (30) on the lower face and a deep, insulated annular groove (32) on the upper face
Implementation Method 2
using an oxide layer to prevent surface inversion
Data Source
Figure 1~3
Figure 4
AI summary
The component has a semiconductor substrate (1) slightly doped with conductivity. A semiconductor layer (3) is provided at a side of an upper face, where the layer is not extended to a periphery of the component. The component periphery has an annular diffused region (30) with another conductivity provided at a side of a lower face. The region is extended to one-third of half of thickness of the component. The component periphery has an insulated annular groove (32) provided at the side of the upper face. The groove traverses the substrate until penetrating into an upper part of the region. The groove is insulated laterally by a silicon oxide layer (33) and filled with non-doped silicon (34).