Vertical Power Device Isolation Wall Trenches
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Solution Overview
Problem
Existing methods for manufacturing vertical power semiconductor devices, such as thyristors, bipolar transistors, and power MOSFETs, face challenges in creating isolation walls with a second conductivity type while maintaining a low resistance path to the conduction region, particularly for three-layer devices which require distinct dopant types for isolation and conduction regions.
Innovation Solution
The process involves forming back and front isolation wall trenches on opposite surfaces of a semiconductor substrate, filling them with a P-type dopant, and then diffusing it to create a continuous isolation wall, while separately forming and filling conduction region trenches with an N-type dopant, ensuring the isolation and conduction regions have appropriate conductivity types without overlapping depths to maintain structural integrity and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same type of dopant is diffused from both isolation wall holes and conduction region holes, then the manufacturing process is simplified, but the device structure cannot support three-layer devices like bipolar transistors and power MOSFETs which require distinct dopant types
Solution Approach 1:
The patent divides the doping process into two separate operations: first diffusing a dopant of second conductivity type to form the isolation wall, then diffusing a dopant of first conductivity type to form the conduction region. This segmentation allows each doping step to be independently controlled, enabling the fabrication of three-layer devices while maintaining process simplicity
Solution Approach 2:
The isolation wall is formed first by diffusing the second conductivity type dopant before forming the conduction region. This preliminary action establishes the isolation structure in advance, preventing contamination of the isolation wall during subsequent conduction region doping, and enables versatile device fabrication
2Device complexity
If isolation wall trenches and conduction region trenches overlap in depth, then manufacturing steps are reduced, but structural integrity and electrical isolation are compromised
Solution Approach 1:
The patent resolves the depth conflict by using horizontal positioning rather than vertical stacking. The conduction region trench is positioned horizontally within the substrate such that its projection does not overlap with the isolation wall trench projection. This dimensional approach maintains both trenches at different horizontal positions while allowing depth optimization, preserving structural integrity and electrical isolation without excessive manufacturing complexity
3Reliability
If a continuous isolation wall is formed by diffusing dopant from isolation wall trenches, then electrical isolation is achieved, but wafer warping may occur due to stress from deep trench diffusion
Solution Approach 1:
The patent applies local quality by making the isolation wall trench depth and doping concentration position-dependent. Trenches at different locations around the conduction region can have different depths and doping levels, allowing the isolation wall to provide sufficient electrical isolation locally while reducing overall stress accumulation that causes wafer warping
Solution Approach 2:
The patent changes the parameters of the isolation wall formation process, specifically controlling the depth, width, and doping concentration of isolation wall trenches. By optimizing these parameters, the patent achieves adequate electrical isolation while minimizing the stress-induced wafer warping that would result from excessively deep or heavily doped trenches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively isolates vertical power devices with low resistance paths, allowing for the fabrication of three-layer devices like bipolar transistors and power MOSFETs, reducing the risk of wafer warping and enhancing manufacturing efficiency by eliminating the need for epitaxial etching and reducing manufacturing costs.
Implementation Method 1
diffusing it to create a continuous isolation wall
Implementation Method 2
filling conduction region trenches with an N-type dopant
Data Source
AI summary
A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region. Thereafter, a film containing a second type dopant is deposited in the front and back isolation wall trenches. In the conduction region on the back surface, conduction region trenches are formed inside the perimeter of the isolation wall trenches. A first type dopant is deposited in the conduction region trenches. The dopants are diffused from the conduction region trenches and isolation wall trenches to form a first conductivity type conduction region structure and a second conductivity type isolation wall.