Vertical Power Transistor Etch Stop Regions

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Solution Overview

Problem

The development of more compact semiconductor devices with increased functionality requires efficient methods for manufacturing thinner vertical power transistors with reduced on resistance, which is primarily influenced by the epitaxial layer resistance.

Innovation Solution

A method involving a semiconductor wafer with selectively formed etch stop regions, where the wafer is doped and etched to create vertical power transistors with contact pads, allowing for precise removal of semiconductor material and application of a metal layer to reduce on resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the wafer is etched thinner to reduce on resistance, then the on resistance decreases, but the risk of etching through the substrate increases

Engineering Contradiction:
Improveon resistanceVSAvoidetching control
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming etch stop regions within the substrate before the main etching process. These regions are created by selectively doping the substrate to form layers with different etch rates, positioned at predetermined depths. During subsequent etching, these pre-formed regions serve as controlled stopping points, ensuring the etch process halts at the desired depth without penetrating through the substrate, thus preventing damage while achieving the required thinness for low on-resistance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop regions function as intermediary layers between the etching process and the substrate. These doped regions have modified etch characteristics that act as a mediator to control the etching depth. The intermediary etch stop layers absorb the variability in etching rates and provide consistent stopping points, allowing precise control of the etching process while maintaining substrate integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If selective doping is used to form etch stop regions, then etching precision improves, but manufacturing complexity increases

Engineering Contradiction:
Improveetching depth controlVSAvoiddoping process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying the physical and chemical properties of the substrate through selective doping. Specific regions are doped with impurities to create layers with different etch rates, electrical properties, and mechanical characteristics. This change in material parameters allows the etching process to naturally stop at predetermined depths without requiring complex real-time monitoring or adjustment mechanisms, thereby achieving high precision while managing manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the manufacturing of thinner vertical power transistors with reduced on resistance, enhancing the performance and efficiency of semiconductor devices while maintaining compact size and reduced costs.

Implementation Method 1

selectively doping the wafer via the first face to selectively form etch stop regions in the wafer

Methodology Applied
Scientific EffectSelective doping: Dopants

Implementation Method 2

etching the wafer at the second face to the etch stop regions

Methodology Applied
Scientific EffectEtching: Ablation

Data Source

PatentUS7923350B2Method of manufacturing a semiconductor device including etching to etch stop regions
Publication Date: 2011.04.12 INFINEON TECHNOLOGIES AG
  • US7923350B2 patent drawing
  • US7923350B2 patent drawing
  • US7923350B2 patent drawing

AI summary

A method of manufacturing a semiconductor device. The method includes providing a wafer having a first face and a second face opposite the first face, selectively doping the wafer via the first face to selectively form etch stop regions in the wafer and etching the wafer at the second face to the etch stop regions.