Vertical Conductive Rail Layout for Dense 3D Integrated Circuits
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Solution Overview
Problem
Integrated circuit devices face challenges in achieving high integration degree and performance due to the trade-off between miniaturization and operation speed, as smaller field effect transistors require complex line structures that can decrease operation speed.
Innovation Solution
The integrated circuit device incorporates a vertical conductive rail with a recessed portion that overlaps an upper contact, allowing for reduced area occupation and improved integration while maintaining electrical connectivity between lower and upper transistors, thereby enhancing integration degree and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If small-sized field effect transistors are used to reduce integrated circuit area, then integration degree is improved, but operation speed decreases due to complex line structure
Solution Approach 1:
The patent transitions from planar 2D transistor layout to 3D vertical architecture by stacking multiple transistor layers (first and second transistor layers) vertically. This dimensional change allows compact area utilization while maintaining efficient electrical pathways through vertical conductive rails, thereby preserving operation speed despite miniaturization.
Solution Approach 2:
The integrated circuit is segmented into multiple functional layers with distinct transistor layers separated by insulating structures. Each layer is independently configured with source/drain regions and conductive rails, allowing optimized electrical pathways for each segment while collectively achieving high integration density without compromising individual transistor performance.
2Area of stationary object
If vertical conductive rail is configured to connect lower and upper contacts, then integration degree is improved, but parasitic capacitance increases
Solution Approach 1:
The vertical conductive rail is segmented into multiple portions (first, second, third portions) separated by insulating structures. This segmentation divides the continuous conductive path into discrete segments, reducing the overall parasitic capacitance by eliminating capacitive coupling along the entire rail length while maintaining electrical connectivity between transistor layers.
Solution Approach 2:
Insulating structures are introduced as intermediary elements between different portions of the vertical conductive rail. These intermediaries electrically isolate adjacent rail segments, preventing parasitic capacitance formation between them, while still allowing the rail portions to serve their connecting function between source/drain regions across different transistor layers.
Data Source
AI summary
An integrated circuit device is provided. The device includes: lower source/drain areas; lower contacts respectively on bottom surfaces of the lower source/drain areas; upper source/drain areas spaced apart from the lower source/drain areas in a vertical direction; upper contacts respectively on upper surfaces of the upper source/drain areas; and a first vertical conductive rail electrically connected to a first contact of the lower contacts and the upper contacts, the first vertical conductive rail extending in the vertical direction, and including a first portion having a first upper surface at a first vertical level and a second portion having a second upper surface at a second vertical level lower than the first vertical level. The second portion overlaps a first upper contact among the upper contacts in the vertical direction.