Vertical Conductive Rail Layout for Dense 3D IC Interconnects
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Solution Overview
Problem
Integrated circuit devices face challenges in achieving high integration degree and performance due to the trade-off between miniaturization and operation speed, as smaller field effect transistors require complex line structures that can decrease operation speed.
Innovation Solution
The integrated circuit device incorporates a plurality of lower and upper source/drain areas with corresponding contacts and vertical conductive rails, where the vertical conductive rail has a recessed portion that overlaps an upper contact, reducing area occupancy and improving integration while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If small-sized field effect transistors are used to reduce integrated circuit area, then the area is reduced, but the operation speed decreases due to complex line structure
Solution Approach 1:
The patent transitions from planar 2D transistor布局 to 3D vertical stacking, where multiple transistor layers are stacked vertically. This dimensional change allows higher integration density without increasing the horizontal footprint, thereby maintaining operation speed while reducing the effective area per transistor through vertical space utilization.
Solution Approach 2:
The patent implements nested vertical stacking where lower and upper transistor layers are positioned one above another, with shared source/drain regions extending vertically. This nesting arrangement allows multiple functional layers to occupy the same horizontal footprint, achieving high integration without proportionally increasing line structure complexity.
2Reliability
If vertical conductive rails are extended to connect lower and upper contacts, then electrical connection is achieved, but parasitic capacitance increases
Solution Approach 1:
The vertical conductive rail is segmented into multiple portions (first portion, second portion, third portion) at different vertical levels. This segmentation allows the rail to be positioned strategically to avoid overlapping with upper contacts, thereby reducing parasitic capacitance while maintaining electrical connectivity between lower and upper transistor layers.
Solution Approach 2:
Instead of extending the vertical conductive rail continuously to the maximum height, the patent inverts the approach by creating recesses or reducing the height of specific portions of the rail. This inversion strategy minimizes the overlapping area with upper contacts, thereby reducing parasitic capacitance while still achieving the necessary electrical connection.
Data Source
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AI summary
An integrated circuit device is provided. The device includes: lower source/drain areas; lower contacts respectively on bottom surfaces of the lower source/drain areas; upper source/drain areas spaced apart from the lower source/drain areas in a vertical direction; upper contacts respectively on upper surfaces of the upper source/drain areas; and a first vertical conductive rail electrically connected to a first contact of the lower contacts and the upper contacts, the first vertical conductive rail extending in the vertical direction, and including a first portion having a first upper surface at a first vertical level and a second portion having a second upper surface at a second vertical level lower than the first vertical level. The second portion overlaps a first upper contact among the upper contacts in the vertical direction.