Vertical Diode-Triggered SCR Layout for Low-Capacitance ESD
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Solution Overview
Problem
Silicon controlled rectifiers (SCRs) used for electrostatic discharge (ESD) protection in integrated circuits face challenges in RF performance due to high capacitance loading and poor harmonics, impacting their effectiveness in high-performance analog and RF designs.
Innovation Solution
A diode triggered silicon controlled rectifier (SCR) structure incorporating a vertical SCR with a doped SiGe region and series-connected vertical diodes, featuring a triggering PN junction and doped SiGe region, to enhance early turn-on and reduce footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SCR is used for ESD protection, then high current handling ability is achieved, but capacitance loading increases and RF performance deteriorates
Solution Approach 1:
The SCR is divided into multiple vertical regions with different doping concentrations and materials (SiGe regions). The device is segmented into p-type and n-type vertical SCR regions, allowing each segment to contribute differently to the overall function, reducing capacitance while maintaining ESD protection capability.
Solution Approach 2:
The patent employs composite semiconductor structures combining silicon and SiGe materials. The SiGe regions are integrated within the SCR structure to modify electrical characteristics, reduce capacitance loading, and improve RF performance while maintaining ESD protection functionality.
2Object-affected harmful factors
If the SCR structure is optimized for low capacitance, then RF performance improves, but ESD protection capability may be compromised
Solution Approach 1:
Different regions of the SCR are assigned different local qualities through varying doping concentrations and SiGe integration. The vertical SCR regions have optimized local properties to reduce capacitance, while the overall structure maintains sufficient current handling ability for ESD protection. The p-type and n-type regions have differentiated local characteristics that collectively solve the contradiction.
3Area of stationary object
If the device footprint is reduced, then integration density increases, but manufacturing complexity may increase
Solution Approach 1:
The patent transitions from a planar device layout to a vertical three-dimensional structure. By stacking multiple doped regions and SiGe layers vertically, the device achieves reduced footprint while accommodating the complex multi-region structure needed for low capacitance and ESD protection functionality.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to diode triggered silicon controlled rectifiers and methods of manufacture. The structure includes: a vertical silicon controlled rectifier (SCR) having a doped semiconductor material region over a semiconductor substrate; and at least one vertical triggering diode electrically connected to the SCR in series, and having a doped semiconductor material region over a doped region in the semiconductor substrate.