Vertical Selection Transistor for 3D Memory Arrays
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Solution Overview
Problem
Current three-dimensional memory devices face challenges such as complex memory cell structures, low storage density, and fabrication difficulties due to the need for high-temperature processing and compatibility issues with silicon substrates in existing selection transistors for RRAM and PCM technologies.
Innovation Solution
A vertical selection transistor is developed using doped polycrystalline semiconductor layers, which allows for a simpler memory cell structure independent of a silicon substrate, with a gate stack controlling the doping concentrations to form a MOS transistor and diode in series, enabling a high on/off current ratio and reducing latch-up effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 1T1R structure with MOS transistor is used for three-dimensional memory, then the memory cell can select or isolate the variable resistor, but the minimum cell area is restricted by the transistor which is unfavorable to high-density three-dimensional stacking
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to vertical 3D stacking by forming memory cells in multiple layers stacked along the vertical direction. Each layer contains complete memory cells with selection transistors, variable resistors, and conductive layers stacked vertically, enabling high-density three-dimensional storage while maintaining the 1T1R selection functionality in each layer.
Solution Approach 2:
The memory structure is segmented into multiple identical layers, each containing a complete 1T1R memory cell. The layers are stacked vertically and separated by isolation layers, allowing independent fabrication and selection of each layer while achieving high-density storage through vertical multiplication of cell units.
2Quantity of substance
If a multi-layer stacked structure is used for three-dimensional memory, then high storage density is achieved, but disturbance between memory cells in the same layer or between different layers occurs
Solution Approach 1:
Isolation layers are inserted between adjacent memory layers to electrically isolate and separate them. These isolation layers prevent current leakage and crosstalk between layers, eliminating disturbance between memory cells in different layers while preserving the multi-layer stacked structure for high storage density.
3Reliability
If monocrystalline silicon diode is used for 1D1R structure, then high forward current density and high rectification ratio are achieved, but high processing temperature is required and it is difficult to fabricate on metal electrode
Solution Approach 1:
The patent changes the material parameter from monocrystalline silicon to polycrystalline silicon for the semiconductor layers. This material substitution maintains the desired electrical properties (forward current density and rectification ratio) while enabling fabrication at lower processing temperatures and compatibility with metal electrode structures, thus resolving the manufacturing difficulty.
4Ease of manufacture
If metal oxide diode is used for 1D1R structure, then good processing compatibility is achieved, but the forward current density is not ideal
Solution Approach 1:
The patent employs a composite structure combining polycrystalline silicon semiconductor layers with metal electrodes and dielectric materials. This composite approach integrates the processing compatibility of metal oxide-based structures with the superior electrical properties (high forward current density and rectification ratio) of polycrystalline silicon diodes, achieving both manufacturing ease and ideal performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution simplifies the memory cell structure, increases storage density, and reduces disturbances and leakage currents between memory cells, enabling a multi-layer stacked structure without the need for high-temperature processing, thus improving the performance and fabrication ease of three-dimensional memory arrays.
Implementation Method 1
a gate stack formed on a side of the second semiconductor layer... so that a vertical MOS transistor is formed by the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the gate stack
Implementation Method 2
a vertical diode is formed by the third semiconductor layer and the fourth semiconductor layer
Data Source
AI summary
The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.