Vertical Semiconductor Devices via Aspect Ratio Trapping
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down device features, reducing channel or external resistance, integrating non-Si channel materials like SiGe and III-V materials onto Si wafers, and improving electron and hole mobility as microelectronic devices approach the 15 nanometer node, particularly in maintaining mobility and short channel control.
Innovation Solution
Aspect ratio trapping (ART) is employed to fabricate vertical semiconductor devices by forming trenches in an insulating layer on a silicon substrate, allowing for the growth of non-lattice-matched materials while trapping defects, enabling defect reduction, gate length scaling, and leakage reduction, and facilitating the integration of III-V and IV materials onto Si substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-Si channel materials such as SiGe and III-V materials are integrated onto Si wafers, then device capacity and performance are improved, but manufacturing complexity and process integration difficulty increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertical 3D channel structures. This dimensional change enables non-Si materials to be integrated on Si wafers by growing vertical channels that can accommodate lattice mismatch through the vertical growth direction, thereby improving device capacity while managing manufacturing complexity through a fundamentally different structural approach
Solution Approach 2:
The patent changes the growth parameters and structural configuration by growing vertical channels with specific crystal orientations and controlling the epitaxial growth conditions. This allows non-Si materials to be integrated onto Si substrates by adjusting growth parameters to accommodate lattice mismatch, improving device performance while maintaining process feasibility
2Productivity
If device dimensions are scaled down to increase density, then chip capacity is improved, but maintaining mobility improvement and short channel control becomes difficult
Solution Approach 1:
The patent uses vertical 3D channel structures instead of planar 2D channels. This dimensional change provides superior short channel control because the gate can wrap around the vertical channel in multiple directions (gate-all-around configuration), enabling effective electrostatic control even at scaled dimensions, thereby maintaining reliability while increasing chip capacity
Solution Approach 2:
The patent employs composite material structures combining different semiconductor materials with specific properties. By using materials with appropriate bandgaps and carrier mobilities in the vertical channel structure, the patent achieves both scaled dimensions for high density and maintained short channel control through material property optimization
3Reliability
If multi-gate transistors and gate-all-around devices are used to reduce channel resistance, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements gate-all-around structures by growing vertical channels and surrounding them with gate material in three dimensions. This dimensional approach reduces channel resistance by providing multiple gate-channel interfaces while managing manufacturing complexity through a systematic vertical growth and deposition process rather than complex planar patterning
Solution Approach 2:
The patent uses a nested structure where the gate completely surrounds the vertical channel, which in turn contains the source and drain regions. This nested configuration achieves low channel resistance through maximum gate control while organizing the complex multi-layer structure in a hierarchical manner that simplifies the manufacturing sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
ART enables the fabrication of high-performance vertical devices with reduced defects, allowing for direct integration of III-V and IV materials, strain-induced mobility enhancement, and efficient leakage reduction, thereby improving transistor performance and density.
Implementation Method 1
Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from
Data Source
AI summary
Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.