Vertical Semiconductor Device Contact Plug Alignment
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Solution Overview
Problem
The existing semiconductor device manufacturing processes face challenges in forming reliable connections between word lines and contact plugs due to misalignment and etching variations, leading to potential substrate damage and contact failures.
Innovation Solution
A vertical type semiconductor device design featuring a pillar structure with word lines and contact plugs, where the insulating interlayer pattern is strategically positioned to reduce misalignment, and the contact plugs are formed using a barrier metal layer and metal layer combination, allowing for simultaneous photolithography processes to minimize etching errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography process is performed multiple times to form connection wires, then wiring connections are established, but manufacturing complexity and failure risk increase
Solution Approach 1:
The patent combines the formation of connection wires and word lines into a single photolithography process step. The insulating interlayer pattern serves as a shared structural element that enables both connection wire formation in the peripheral circuit region and word line formation in the cell array region simultaneously, reducing the number of photolithography steps from multiple separate processes to a unified process.
Solution Approach 2:
The insulating interlayer pattern performs multiple functions: it provides electrical isolation in the peripheral circuit region, serves as a structural support for contact plugs, and enables word line formation in the cell array region. This multi-functional design allows a single structure to facilitate both connection wire and word line formation without requiring separate dedicated structures for each function.
2Reliability
If contact plugs are formed to connect substrate and word lines, then electrical connections are established, but misalignment and etching variations cause contact failures
Solution Approach 1:
The insulating interlayer pattern is formed in advance before contact plug formation, establishing a predefined structural framework. The pattern's top surface is positioned at a specific height relative to the pillar structure, creating predetermined alignment references that guide subsequent contact hole formation and ensure accurate contact plug placement, thereby compensating for potential alignment variations.
Solution Approach 2:
The insulating interlayer pattern acts as an intermediary structure between the substrate and the contact plugs. By positioning its top surface at a specific height, it provides a stable reference plane that mediates the alignment between the contact plugs and the underlying substrate features, reducing the direct impact of etching variations on alignment precision.
3Adaptability or versatility
If insulating interlayer pattern is positioned at different heights, then structural flexibility is achieved, but misalignment between contact plugs and word lines occurs
Solution Approach 1:
The patent specifies a precise parameter for the insulating interlayer pattern's top surface height: it is positioned between the upper and lower word lines at a height that ensures the edges of the word lines are exposed at contact holes. This controlled parameter change optimizes both the structural flexibility needed for different device configurations and the alignment precision required for reliable contact formation.
Data Source
AI summary
A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced.