Vertical Semiconductor Integration via Epitaxial Silicon Stacking
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Solution Overview
Problem
Current semiconductor chip fabrication processes face challenges in achieving higher integration levels, leading to increased costs and complexity, as well as the need for more compact and functionally advanced electronic devices.
Innovation Solution
A vertically integrated semiconductor device is formed using a single crystal silicon substrate with multiple vertically spaced single crystal silicon layers, interconnected by tungsten or polysilicon leads, achieved through an epitaxial growth process and dielectric layer formation, allowing for increased semiconductor device integration and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are used to achieve higher integration levels, then device functionality increases, but device size and complexity increase
Solution Approach 1:
The patent transitions from horizontal integration (multiple chips side-by-side) to vertical integration (multiple single crystal silicon layers stacked vertically). This dimensional change allows multiple functional layers to be integrated within a compact footprint, achieving high functionality without proportionally increasing device size. The vertical stacking of active regions, interconnect layers, and dielectric layers enables three-dimensional device architecture that consolidates multiple chip functions into a single vertically-integrated structure.
2Adaptability or versatility
If conventional fabrication processes are used to increase integration levels, then more functions are achieved, but production costs increase
Solution Approach 1:
The patent merges multiple fabrication processes into a unified epitaxial growth approach. Instead of separately fabricating multiple chips and assembling them, the invention uses sequential epitaxial growth to form multiple single crystal silicon layers with integrated active regions, interconnects, and dielectric materials in a single continuous process. This consolidation reduces the number of discrete fabrication steps, minimizes assembly operations, and lowers overall production costs while achieving high integration levels.
Solution Approach 2:
The patent employs parameter changes in the epitaxial growth process to control the formation of different layers and structures. By adjusting growth conditions (temperature, pressure, gas flow, dopant concentration) during sequential epitaxial growth, the process can produce varied functional layers (n-type, p-type, intrinsic regions) and structural features (active regions, interconnect pathways, isolation structures) within a unified manufacturing approach, reducing the need for multiple specialized fabrication processes.
3Adaptability or versatility
If more semiconductor chips are assembled to increase functionality, then device capabilities improve, but the number of components and assembly complexity increase
Solution Approach 1:
The patent combines multiple chip functions into a single vertically-integrated device structure. By stacking multiple single crystal silicon layers with embedded active regions, interconnect layers, and dielectric materials, the invention consolidates what would traditionally require multiple separate chips into one unified component. This merging reduces the total number of discrete components, simplifies assembly operations, and decreases packaging complexity while maintaining or enhancing device capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of more compact electronic devices with increased functionality by forming multiple layers of single crystal silicon, reducing the number of semiconductor chips required and enhancing integration levels, thereby lowering production costs and improving device performance.
Implementation Method 1
performing an epitaxial growth process in which the openings act as seed windows where the epitaxial growth begins
Data Source
AI summary
A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.