Vertical Semiconductor Device Segmentation for Operational Control
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Solution Overview
Problem
As the number of stacked memory cells in vertical memory devices increases, operational control becomes challenging, leading to inefficiencies in device performance.
Innovation Solution
A semiconductor device design featuring base layer patterns separated by a separation layer, with vertically extending channels and gate lines, allowing for independent operation and segmentation of cell blocks, enabling improved operational efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stacked number of memory cells is increased to achieve high degree of integration, then the integration density is improved, but the operational control becomes difficult
Solution Approach 1:
The base layer is divided into multiple independently controllable base layer patterns (first base layer pattern, second base layer pattern, etc.), each capable of receiving different voltages. This segmentation allows selective control of different memory cell blocks, resolving the operational control difficulty while maintaining high integration density through vertical stacking.
2Quantity of substance
If more memory cells are stacked vertically, then the storage capacity is improved, but the signal interference increases
Solution Approach 1:
By dividing the base layer into separate base layer patterns that can be independently voltage-controlled, the patent enables selective operation of different memory cell blocks. This reduces signal interference between vertically stacked cells by isolating their control signals, while still achieving high storage capacity through vertical stacking.
Solution Approach 2:
Different base layer patterns can receive different voltages (e.g., first voltage for first base layer pattern, second voltage for second base layer pattern), allowing localized control of electrical properties in different regions. This local quality control reduces signal interference while maintaining high storage capacity through vertical integration.
Data Source
AI summary
A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.