Vertical Semiconductor Device With Stacked Gate Electrodes
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high integration density and reliability due to complex wiring structures required for reduced memory cell sizes, which complicates manufacturing processes.
Innovation Solution
A semiconductor device design featuring gate electrodes stacked perpendicular to the substrate, with first and second channels penetrating through and connecting to a source line, and including ground select and string select transistors, allowing for improved electrical connections and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to achieve high integration density, then integration density is improved, but wiring structure becomes more complex
Solution Approach 1:
The patent transitions from planar wiring structures to three-dimensional vertical channel structures with stacked gate electrodes. Memory cells are arranged in vertical stacks penetrating through the substrate, allowing integration density to increase in the vertical dimension rather than requiring more complex planar wiring. This dimensional change enables high integration density while maintaining relatively simple wiring connectivity.
Solution Approach 2:
The patent implements nested structures where channels penetrate through multiple stacked gate electrodes, and select electrodes are positioned at different vertical levels within the stack. The horizontal portion connects channels at lower levels, creating a nested arrangement where smaller functional elements are contained within larger structural frameworks, enabling compact integration without excessive wiring complexity.
2Ease of manufacture
If wiring structure is simplified to ease manufacturing, then ease of manufacture is improved, but integration density may be reduced
Solution Approach 1:
By moving to vertical stacking architecture, the patent achieves high integration density through the vertical dimension rather than through complex planar interconnects. This simplifies manufacturing because the vertical stacks can be formed using standard deposition and etching processes, and wiring connections are made through vertical vias rather than complex lateral routing.
Solution Approach 2:
The patent divides the memory structure into discrete stacked units with standardized components (channels, gate electrodes, select electrodes). Each stack is an independent modular unit that can be manufactured using repeatable processes, facilitating ease of manufacture while achieving high integration density through the repetition of these standardized segments.
3Quantity of substance
If gate electrodes are stacked vertically, then integration density is improved, but device structure becomes more complex
Solution Approach 1:
The vertical stack structure serves multiple functions simultaneously: the stacked gate electrodes act as both storage cell gates and select line gates, the channels provide both data storage pathways and selection pathways, and the horizontal portion provides both structural support and electrical connection. This multi-functionality reduces the need for separate dedicated structures, thereby improving integration density without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the functions of multiple gate electrodes into a single vertical stack, combining what would traditionally be separate planar gates into one integrated three-dimensional structure. The select electrodes are merged with the memory cell gates in the same vertical stack, and the channels serve both as storage elements and as selection elements, reducing overall structural complexity while maintaining high integration density.
Data Source
AI summary
A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.