Vertical SiP RF Componentry for Compact Wireless Footprint
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Solution Overview
Problem
Traditional multi-chip modules (MCMs) face challenges in miniaturization due to large system-on-a-chip (SoC) and crystal components, leading to increased parasitic capacitance and footprint, which hinders the development of smaller wireless devices with greater functionality.
Innovation Solution
The implementation of a system-in-a-package (SiP) with vertical integration of SoCs and discrete components, including crystals, using a substrate for interconnections, reduces package size and parasitic capacitance by stacking components, such as crystals and load capacitors, over the SoC, and utilizing wire bonds or solder bumps for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-chip module (MCM) design is used with horizontal arrangement of SoC and crystal components, then the device provides complete RF functionality, but the package footprint becomes large and parasitic capacitance increases
Solution Approach 1:
The patent transitions from a two-dimensional horizontal arrangement of components to a three-dimensional vertical stacking architecture. The SoC, crystal, and other RF components are arranged in multiple layers stacked vertically, with interconnections achieved through through-silicon vias (TSVs) and wire bonds. This dimensional change dramatically reduces the package footprint while maintaining complete RF functionality, directly resolving the contradiction between functional completeness and compact size.
2Reliability
If traditional MCM design with long crystal routing paths is used, then the crystal can be properly connected to the SoC, but parasitic capacitance increases and oscillation startup capability is adversely affected
Solution Approach 1:
By stacking the crystal vertically above the SoC and using through-silicon vias for interconnection, the patent dramatically shortens the signal path length compared to horizontal routing. This vertical integration reduces parasitic capacitance to minimal levels, ensuring reliable crystal oscillation startup while maintaining proper electrical connections between components.
3Area of stationary object
If vertical stacking of components is implemented in SiP design, then package footprint is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the RF system into separate functional modules (SoC, crystal, FEM, LNA) that can be manufactured and tested independently before final assembly. This segmentation allows each component to be optimized separately and simplifies the manufacturing process by enabling modular assembly, thereby reducing the overall manufacturing complexity despite the vertical stacking architecture.
Solution Approach 2:
The patent introduces a substrate as an intermediary platform that facilitates the vertical stacking of components. The substrate provides mechanical support, electrical interconnections through TSVs, and thermal management pathways. This intermediary structure simplifies the integration process by providing standardized interfaces and connection methods, reducing the complexity of direct component-to-component bonding.
4Ease of manufacture
If horizontal arrangement of crystal and SoC is used in MCM, then manufacturing is simpler, but crystal trace routing adds significant parasitic capacitance
Solution Approach 1:
The patent eliminates the need for long horizontal crystal trace routing by stacking the crystal vertically above the SoC. The interconnection is achieved through vertical TSVs and wire bonds, reducing the trace length to minimal dimensions. This dimensional change drastically reduces parasitic capacitance while the modular stacking approach maintains ease of manufacture through standardized vertical assembly processes.
Data Source
AI summary
A packaged module for use in a wireless communication device has a substrate supporting a first integrated circuit die that implements at least a portion of a radio frequency baseband subsystem and a second integrated circuit die that implements at least a portion of a radio frequency front end including a radio frequency power amplifier. The substrate is disposed between the first integrated circuit die and the second integrated circuit die. An overmold encloses one of the first integrated circuit die and the second integrated circuit die.