Vertical Spiral Inductor Reducing Silicon Area
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Solution Overview
Problem
Conventional planar spiral inductors occupy a large silicon area and are affected by magnetic fields, limiting their integration density and performance in semiconductor devices.
Innovation Solution
A vertical spiral inductor structure is developed, where through holes in a substrate connect a metal interconnect structure on the top surface to a redistribution layer on the bottom surface, reducing the silicon area occupied and minimizing the impact of magnetic fields, with a method involving the formation of through-silicon vias and metal layers to create a compact, efficient inductor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar spiral inductor structure is used, then the inductor can be formed with conventional metal layers, but it occupies a large silicon area
Solution Approach 1:
The patent transitions from a planar (2D) spiral inductor structure to a vertical (3D) structure by stacking metal layers in the vertical direction and connecting them through vias. This dimensional change allows the inductor to achieve the required inductance value with significantly reduced footprint area, as the magnetic path extends vertically through multiple layers rather than spreading horizontally in a single plane.
2Device complexity
If a planar spiral inductor is used, then the structure is simple, but it is affected by magnetic fields from active areas and polysilicon layers
Solution Approach 1:
By moving the inductor structure to the vertical dimension with stacked metal layers, the patent spatially separates the inductor from planar magnetic field sources such as active areas and polysilicon layers. This vertical stacking creates physical distance and different spatial planes, reducing magnetic coupling and interference from conventional planar device layers.
Solution Approach 2:
The patent embeds the inductor structure within the three-dimensional IC architecture, nesting the vertical inductor among other device layers. The inductor is integrated into the vertical stack of metal layers and dielectric structures, allowing it to coexist with other components while minimizing magnetic interference through spatial arrangement and shielding provided by surrounding structures.
3Productivity
If the memory cell structure is reduced to increase integration density, then more memory capacity can be achieved, but the area available for passive devices like inductors is reduced
Solution Approach 1:
The vertical inductor structure utilizes the third dimension (vertical stacking) to achieve the required inductance value, thereby dramatically reducing the horizontal footprint. This enables high integration density by allowing inductors to be placed in previously unavailable vertical space, accommodating more memory cells per unit area while still providing sufficient area for passive devices.
Data Source
AI summary
A method of fabricating a spiral inductor includes providing a substrate having a top surface and a bottom surface, forming a plurality of through holes aligned in a vertical plane and spaced apart from each other, forming a metal interconnect structure having at least one top metal layer on the top surface of the substrate, the metal interconnect structure configured to connect to a top portion of the through holes, and forming a redistribution layer having at least a bottom layer on the bottom surface of the substrate. The redistribution layer is configured to connect to a bottom portion of the through holes to form a spiral structure.