Printed Inductances TRIZ Cases
- Thick Surface Conductor Layout for Wider Trimming Adjustment
Thicker surface conductors than internal layers enable easier trimming, broader electrical adjustment, smaller components, and resin protection.
- Stacked Glass Package Substrates for Thermal Stress and Power Delivery
Stacked glass layers with different CTEs and buffer materials limit crack growth while CMILs and PMVs maintain power delivery through the substrate.
- Flexible Coil Substrate Layout for High Space Factor Motors
A controlled wiring width and T1/T2 coating ratio helps coil substrates prevent shorts while preserving space factor and lowering motor losses.
- Laminated Coil Layout for Precise Inductance Adjustment
By shifting the relative lamination position of coil layers, this case tunes inductance precisely while reducing short-circuit risk and flux obstruction.
- Multi-Lobe On-Chip Inductor Layout for Mutual Coupling Isolation
A ground ring and broken ring terminate magnetic flux around a multi-lobe on-chip inductor, reducing mutual coupling without extra silicon area.
- Coaxial Via Inductor Dual-Magnetic Ring Structure for Higher Inductance
A dual-magnetic ring around a conductive through-core via boosts inductance density and current capacity in package substrates.
- Directional Coupler Inductor Layout for Compact High Coupling
Opposed inductor and line sections boost electromagnetic coupling in a compact directional coupler while maintaining isolation.
- Stacked Spiral Inductor Structure for High-Frequency ICs
A stacked spiral inductor structure uses multiple metal layers and vias to form shunt windings.
- Laminate Inductor With Magnetic Gap Layers For Saturation Control
Segmenting the magnetic flux path with non-magnetic gap layers prevents saturation, ensuring stable inductance and improved DC-superimposed characteristics.
- Inductor-Embedded Substrate Manufacturing via Magnetic Paste Segmentation
Segmenting iron powder into a dedicated layer protects it from etching degradation while maintaining high inductance.
- Vertical Spiral Inductor Reducing Silicon Area
Vertical spiral inductors reduce silicon area by stacking metal layers through vias, minimizing magnetic field interference from planar device components.