Vertical String Drivers in 3D NAND Memory
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Solution Overview
Problem
In 3D NAND flash memory devices, the large area occupied by string driver transistors limits die size and efficiency due to their placement under the memory array, causing congestion and inefficiencies in the CUA space, especially as the number of wordline tiers increases.
Innovation Solution
The string drivers are relocated from the CUA space and integrated vertically into a semiconductor layer on top of the wordline stack, using polysilicon or CAAC-IGZO transistors, which reduces the need for metal routing and frees up die space by positioning them perpendicular to the tier stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If string driver transistors are placed in the CUA space under the memory array, then they can provide gate connections for wordlines, but they occupy significant die area and cause congestion especially as wordline tiers increase
Solution Approach 1:
The patent moves string driver transistors from the planar CUA space (2D placement) to the vertical dimension by forming them in a semiconductor layer on top of the memory array. This dimensional transition allows gate connections to be made through vertical vias and conductive layers, resolving the area congestion problem while maintaining connection reliability.
Solution Approach 2:
The string driver transistors are extracted from the CUA space and relocated to the semiconductor layer above the memory array. This separation removes the congesting elements from the problematic area while preserving their essential function of providing gate connections to wordlines through vertical interconnect structures.
2Reliability
If more string driver transistors are added to support high voltage and breakdown conditions, then device performance is improved, but the occupied area increases significantly
Solution Approach 1:
By forming string driver transistors in the vertical semiconductor layer rather than spreading them across the planar CUA space, the patent enables high voltage support capabilities while minimizing die area occupation. The vertical stacking allows multiple transistors to share the same footprint through three-dimensional integration.
Solution Approach 2:
The string driver transistors are nested within the vertical semiconductor structure, with multiple transistor layers stacked above the memory array. This nesting arrangement allows multiple high-voltage capable transistors to occupy a compact volume rather than requiring extensive planar space.
3Ease of operation
If string driver transistors are disposed in the CUA space, then they can access wordlines, but contact area availability and block height dimensions are affected
Solution Approach 1:
The patent resolves the conflict between wordline access ease and block height by moving transistor placement to the vertical dimension. Wordline access is maintained through vertical vias and conductive layers that connect the semiconductor layer transistors to the memory array, while block height is optimized by consolidating the transistor structure above the array rather than extending it laterally.
Data Source
AI summary
Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.