Vertical TFET Cell Structure for Low-Leakage Drain Contact Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing tunneling field-effect transistors (TFETs) face challenges in reducing off-state leakage currents and power usage due to scaling limitations, as feature sizes decrease and signal crossovers become more prominent in semiconductor integrated circuits.
Innovation Solution
A method for fabricating TFET devices involves forming a frustoconical protrusion structure on a substrate, with a gate stack that wraps around the protrusion and overlaps with a raised drain region, and forming contacts on isolation features to reduce contact resistance and active area, utilizing high-k/metal gate and polysilicon gate stacks with specific dielectric layers and doping processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOS field-effect transistors are used, then device scaling is achieved, but off-state leakage currents increase and power usage becomes significant
Solution Approach 1:
The patent changes the fundamental operating mechanism of the transistor from conventional MOS to tunneling field-effect transistor (TFET), utilizing quantum tunneling effects to achieve sub-60 mV/dec subthreshold swing. This parameter change enables the device to maintain low off-state leakage currents while achieving further scaling, directly resolving the contradiction between device scaling and leakage current control
Solution Approach 2:
The patent transitions from planar device architecture to vertical tunneling field-effect transistor structure, adding the vertical dimension to the device geometry. This dimensional change allows for better gate control over the channel and reduced leakage paths, enabling continued scaling without proportional increases in off-state leakage
2Area of stationary object
If feature sizes are decreased to increase interconnected devices per unit area, then circuit density improves, but current leakage and signal crossover become more noticeable
Solution Approach 1:
By transitioning to vertical device architecture, the patent reduces the footprint area of each transistor while maintaining or improving performance. The vertical structure provides better isolation between adjacent devices, reducing signal crossover, and the confined channel geometry reduces leakage paths, thereby achieving higher circuit density without increasing harmful effects
Solution Approach 2:
The patent implements localized doping regions and material compositions within the vertical TFET structure, creating specific zones with optimized electrical properties. This local quality control enables precise management of carrier transport and leakage currents in different regions of the device, reducing harmful effects while maintaining high density
3Loss of energy
If TFETs are used to enable further scaling without increasing off-state leakage, then power usage is reduced, but existing TFET structures are not satisfactory in every respect
Solution Approach 1:
The patent employs composite material structures in the vertical TFET, including high-k dielectric materials for gate insulation, metal gate electrodes, and carefully engineered semiconductor layers with different bandgaps. These composite materials work together to achieve both low power consumption through reduced leakage and high reliability through improved device characteristics and stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces drain contact resistance, minimizes the active device area, and relaxes contact lithography constraints, enabling more efficient power management and further scaling of power supply voltage without increasing off-state leakage currents.
Implementation Method 1
a gate stack (510) having a planar portion (512), which is parallel to a surface of the substrate (210), and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure (220)
Implementation Method 2
utilizing high-k/metal gate and polysilicon gate stacks with specific dielectric layers
Data Source
AI summary
A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.