Vertical TFET Self-Aligned Heterojunction via Oxide Spacers
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Solution Overview
Problem
Implementing a self-aligned heterojunction in a vertical gate-all-around architecture for tunnel field effect transistors (TFETs) is challenging due to the need for precise junction overlap control, which is essential for achieving abrupt turn-on and increased drive current, while existing methods often result in underlapped or overlapped junctions, degrading performance.
Innovation Solution
A method is developed to integrate a self-aligned heterojunction in a vertical gate-all-around TFET architecture by forming doped silicon germanium (SiGe) layers on a silicon substrate, creating fins with a heterojunction, and using a low-temperature oxidation process to selectively form oxide spacers along the SiGe portion of the fins, which self-aligns the gate stack with the heterojunction, thereby ensuring precise junction alignment without additional masking or patterning steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form the gate stack, then the fabrication process is simpler, but the junction alignment is imprecise resulting in underlapped or overlapped junctions that degrade performance
Solution Approach 1:
Oxide spacers are formed on the SiGe portion of the fins before the gate stack is deposited. This preliminary formation of spacers establishes the precise alignment reference for the subsequent gate stack, ensuring the gate is correctly positioned relative to the heterojunction without requiring complex post-alignment steps
Solution Approach 2:
Oxide spacers serve as an intermediary structure between the SiGe source region and the gate stack. These spacers act as a physical reference that mediates the alignment process, allowing the gate stack to be self-aligned to the heterojunction through a straightforward deposition process rather than complex patterning
2Power
If the tunneling barrier width is reduced to increase drive current, then the drive current increases, but the junction alignment must be extremely precise to maintain abrupt turn-on
Solution Approach 1:
The oxide spacers automatically define the gate position relative to the SiGe source region through their formation process. The gate stack subsequently deposits conformally on the spacer structure, self-aligning itself to the heterojunction without requiring external alignment references or complex patterning steps, thus achieving precise alignment even with reduced barrier widths
3Reliability
If a self-aligned heterojunction is implemented to achieve abrupt turn-on and increased drive current, then the device performance improves, but the fabrication process becomes more complex
Solution Approach 1:
Oxide spacers are introduced as an intermediary structure that simplifies the overall fabrication complexity. Rather than requiring complex multi-step alignment procedures, the spacers provide a straightforward geometric reference that guides gate stack formation through simple conformal deposition, achieving self-alignment in an additional process step
Solution Approach 2:
The oxide spacers are formed in advance before gate stack deposition, establishing the alignment geometry early in the process. This preliminary structuring allows subsequent steps to proceed with simpler, more robust processes while maintaining precise alignment, effectively trading one process step for improved overall process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a high percentage germanium source with an abrupt junction, reducing the effective tunneling barrier width and enhancing drive current without defect generation, while maintaining compatibility with baseline vertical MOSFET process flows.
Implementation Method 1
using a low-temperature oxidation process to selectively form oxide spacers along the SiGe portion of the fins
Data Source
AI summary
Techniques for integrating a self-aligned heterojunction for TFETs in a vertical GAA architecture are provided. In one aspect, a method of forming a vertical TFET device includes: forming a doped SiGe layer on a Si substrate; forming fins that extend through the doped SiGe layer and partway into the Si substrate such that each of the fins includes a doped SiGe portion disposed on a Si portion with a heterojunction therebetween, wherein the SiGe portion is a source and the Si portion is a channel; selectively forming oxide spacers, aligned with the heterojunction, along opposite sidewalls of only the doped SiGe portion; and forming a gate stack around the Si portion and doped SiGe that is self-aligned with the heterojunction. A vertical TFET device formed by the method is also provided.