Vertical TFET Structure With Leveled Source-Drain Contacts
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Solution Overview
Problem
Conventional CMOSFET scaling faces challenges with rapid power consumption increases, and vertical TFETs present difficulties due to the height difference between source and drain, complicating contact formation.
Innovation Solution
A vertical TFET structure and method are developed, involving a semiconductor substrate with patterned hard masks, selective recessing, and ion implantation to form mesas and isolation features, enabling a vertically configured channel between source and drain, and subsequent gate and contact formation to address the height difference and improve fabrication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If vertical TFET structure is used to enable further scaling of power supply voltage, then power consumption is reduced, but contact formation becomes more difficult due to height difference between source and drain
Solution Approach 1:
The patent transitions from a planar TFET structure to a vertical three-dimensional structure, where the channel extends vertically between source and drain regions at different horizontal levels. This dimensional change enables continued scaling benefits while managing the inherent contact formation challenges through specialized contact structures that accommodate the vertical architecture.
Solution Approach 2:
The patent divides the contact formation process into separate stages: first forming contacts to the drain region at a higher level, then forming contacts to the source region at a lower level. This segmentation allows each contact to be optimized independently for its specific vertical position, resolving the manufacturing difficulty caused by the height difference.
2Productivity
If conventional CMOSFET scaling is continued, then device density is improved, but power consumption increases rapidly
Solution Approach 1:
The patent changes the fundamental operating parameter of the transistor by switching from conventional CMOSFET to tunnel field effect transistor (TFET) operation. TFETs utilize band-to-band tunneling mechanisms that enable sub-60mV/dec subthreshold swing, allowing power supply voltage scaling below conventional limits while maintaining device density through vertical channel structures.
3Shape
If source and drain are at different horizontal levels in vertical TFET, then vertical channel structure is achieved, but fabrication complexity increases
Solution Approach 1:
The patent performs preliminary actions by first forming the drain region and its contacts at the higher horizontal level before forming the source region and its contacts at the lower level. This sequential preliminary formation simplifies the overall fabrication process by establishing the vertical architecture step-by-step rather than attempting to form all features simultaneously.
Solution Approach 2:
The patent introduces intermediate structures such as dielectric layers and etch stop layers between the source and drain regions. These intermediary elements facilitate the vertical separation of source and drain at different horizontal levels while providing structural support and enabling selective etching and deposition processes during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for effective scaling of power supply voltage without increasing off-state leakage current, facilitating reliable and cost-effective contact formation and improved device performance by leveling the source and drain, thus enhancing the reliability and performance of TFET devices.
Implementation Method 1
performing a first implantation to form a drain of a first type conductivity, wherein the drain is a continuous doped feature extended from the first semiconductor mesa to the second semiconductor mesa through the semiconductor substrate; and performing a second implantation to form a source having a second type conductivity opposite to the first type conductivity
Data Source
AI summary
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.